Nanosheet Channel Structures with Thin Silicon Work-Function Layers
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Solution Overview
Problem
The challenge in semiconductor manufacturing is achieving further down-scaling of transistors while maintaining effective gate control, as traditional aluminum-containing work function adjustment layers hinder size reduction due to their thickness requirements.
Innovation Solution
Employing a silicon-containing work function adjustment layer with a reduced thickness, which allows for the formation of nanosheet channel structures in gate-all-around transistors, enabling further down-scaling without compromising gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If aluminum-containing work function adjustment layers are used, then the desired work function is achieved, but the layer thickness increases hindering device down-scaling
Solution Approach 1:
The patent changes the material composition parameter of the work function adjustment layer from aluminum-containing to silicon-containing material. This parameter change enables the layer to achieve the desired work function (4.05 eV to 4.25 eV) with a reduced thickness of 5 nm to 15 nm, thereby resolving the contradiction between achieving the target work function and minimizing layer thickness for device down-scaling
Solution Approach 2:
The patent employs a composite structure consisting of a high-k dielectric layer (first material layer) and a silicon-containing work function adjustment layer (second material layer). The high-k dielectric layer provides gate control while the thin silicon-containing layer adjusts the work function. This composite approach allows the gate structure to achieve both effective channel control and appropriate work function with overall reduced thickness, enabling further device down-scaling
Data Source
AI summary
The present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a first nanosheet channel structure and a first high-k dielectric layer surrounding the first nanosheet channel structure. In addition, the semiconductor structure includes a second nanosheet channel structure disposed above and substantially parallel to the first nanosheet channel structure, and a second high-k dielectric layer surrounding the second nanosheet channel structure. The semiconductor structure further includes a work function adjustment layer including silicon and disposed between the first high-k dielectric layer and the second high-k dielectric layer. The first high-k dielectric layer and the second high-k dielectric layer are separated by the work function adjustment layer.


