Stacked GAA Channels with Anti-Punch-Through Dopant Control
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Solution Overview
Problem
Existing multigate devices, such as gate-all-around (GAA) devices, face challenges in forming anti-punch-through features effectively, leading to dopant diffusion and degradation of mobility and device performance, particularly in high mobility channels.
Innovation Solution
The fabrication method includes forming doped wells and anti-punch-through (APT) features with specific doping concentrations and configurations, followed by a prebaking process to improve crystal quality, and using a diffusion blocking layer to prevent dopant diffusion, combined with epitaxial growth of semiconductor layers to create a semiconductor layer stack with alternating compositions for enhanced gate control and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-punch-through features are formed in conventional GAA devices, then dopant diffusion is reduced, but the features cannot be properly formed leading to manufacturing failures
Solution Approach 1:
The patent divides the channel structure into multiple discrete nanowire or nanosheet channels stacked vertically, each surrounded by its own gate structure. This segmentation allows the gate to control each channel independently and prevents the formation of parasitic mesa devices that plague conventional GAA structures, thereby enabling proper APT feature formation while maintaining dopant retention.
Solution Approach 2:
The patent transitions from planar or simple vertical GAA structures to a three-dimensional stacked configuration where channels are arranged vertically and surrounded gates wrap around them. This dimensional change provides better gate control over the channel region, enables proper APT feature formation, and eliminates the manufacturing issues associated with conventional approaches.
2Reliability
If doping concentration is increased to improve dopant retention, then mobility degradation occurs due to dopant diffusion in the channel region
Solution Approach 1:
The patent applies different doping concentrations to different regions: heavily doped source and drain regions for carrier injection and collection, while maintaining low or zero doping in the channel region to preserve carrier mobility. The gate-all-around structure enables this local differentiation by providing superior control over the channel, preventing unwanted dopant diffusion that would otherwise require higher doping concentrations.
Solution Approach 2:
The gate structure acts as an intermediary that controls the electric potential in the channel region, enabling the device to maintain low channel doping while achieving the necessary carrier concentration at the source and drain through the surrounded gate control. This mediator effect allows decoupling of dopant retention requirements from mobility preservation.
3Length of moving object
If channel dimensions are reduced to enable aggressive scaling, then gate control is maintained, but anti-punch-through features cannot be properly formed
Solution Approach 1:
The patent employs a three-dimensional gate-all-around configuration where the gate wraps around the channel from all directions (top, bottom, and sidewalls). This dimensional approach maintains effective gate control even as channel length is reduced for scaling, while the surrounded structure provides the necessary geometric configuration to properly form APT features without the manufacturing issues of planar approaches.
Solution Approach 2:
The patent utilizes composite material structures including semiconductor nanowires or nanosheets combined with high-k dielectric gate materials and metal gate electrodes. This composite approach enables aggressive channel scaling while maintaining gate control and providing the structural integrity needed for proper APT feature formation in scaled devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances dopant retention and suppresses parasitic mesa device leakage, improving the performance and reliability of multigate devices by maintaining gate control and reducing short-channel effects.
Implementation Method 1
a prebaking process to improve crystal quality
Implementation Method 2
using a diffusion blocking layer to prevent dopant diffusion
Implementation Method 3
epitaxial growth of semiconductor layers to create a semiconductor layer stack with alternating compositions
Data Source
AI summary
The present disclosure provide a method that includes receiving a substrate having a semiconductor surface of a first semiconductor material; forming an APT feature in the substrate; performing a prebaking process to the substrate with a first temperature T1; epitaxially growing an undoped semiconductor layer of the first semiconductor layer and a first thickness t1 on the substrate at a second temperature T2; epitaxially growing a semiconductor layer stack over the undoped semiconductor layer at a third temperature T3 less than T2, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration; patterning the semiconductor substrate, and the semiconductor layer stack to form a trench, thereby defining an active region being adjacent the trench; forming an isolation feature in the trench; selectively removing the second semiconductor layers; and forming a gate structure wrapping around each of the first semiconductor layers.