Display Polishing Slurry for Oxide-Nitride Planarization
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Solution Overview
Problem
Display devices with inorganic insulation layers often have uneven surfaces, leading to reduced capacitance and potential disconnections or skew issues due to the formation of capacitor electrodes on these uneven layers.
Innovation Solution
A polishing slurry comprising polishing particles, a dispersing agent, an oxide-polishing promoter, and a nitride-polishing inhibitor is used to planarize the insulation layers, specifically formulated to have a high selectivity for silicon oxide over silicon nitride, ensuring a flat surface and reducing residual distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional polishing slurries are used on insulation layers with stacked silicon oxide and silicon nitride, then polishing can be performed, but the polishing selectivity between silicon oxide and silicon nitride is insufficient, resulting in uneven surfaces and residual distribution
Solution Approach 1:
The patent changes the chemical composition parameters of the polishing slurry by introducing specific promoters and inhibitors. The oxide polishing promoter (e.g., HF, HCl) increases the polishing rate of silicon oxide, while the nitride polishing inhibitor (e.g., ammonia, amine compounds) decreases the polishing rate of silicon nitride, thereby achieving high selectivity and improved surface planarity
Solution Approach 2:
The patent creates a composite polishing slurry system that combines multiple functional components: polishing particles (ceria, silica, alumina), dispersing agents (polymer-based or surfactant-based), oxide promoters, and nitride inhibitors. This composite formulation enables simultaneous control of polishing rate and selectivity between different inorganic materials
2Reliability
If the insulation layer surface is not planarized, then the manufacturing process is simpler, but the capacitance is reduced and disconnections or skew may occur due to uneven surfaces
Solution Approach 1:
The patent performs planarization of the insulation layer surface before forming the capacitor electrode. By using the specialized polishing slurry to create a flat surface in advance, subsequent electrode formation can proceed without defects, ensuring reliable electrical connections and preventing disconnections or skew issues
3Manufacturing precision
If high polishing selectivity is achieved through complex slurry formulation, then surface planarity is improved, but the slurry composition and process control become more complex
Solution Approach 1:
The patent uses chemical intermediaries in the form of promoters and inhibitors that mediate the polishing reaction. The oxide promoter acts as a catalyst to enhance silicon oxide removal, while the nitride inhibitor acts as a protective agent to reduce silicon nitride removal, enabling selective polishing without requiring complex mechanical or process controls
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The polishing slurry effectively planarizes the insulation layers, enhancing profile uniformity and reducing defects like disconnections, while allowing for efficient design with reduced line widths.
Implementation Method 1
a polishing slurry includes about 0.01 wt % to about 10 wt % of polishing particles
Implementation Method 2
about 0.005 wt % to about 0.1 wt % of a dispersing agent
Data Source
AI summary
A polishing slurry is disclosed which includes about 0.01 wt % to about 10 wt % of polishing particles, about 0.005 wt % to about 0.1 wt % of a dispersing agent, about 0.001 wt % to about 1 wt % of an oxide-polishing promoter including a pyridine compound, about 0.05 wt % to about 0.1 wt % of a nitride-polishing inhibitor including an amino acid or an anionic organic acid, and water. A method for manufacturing a display device including an active pattern disposed on a base substrate, a gate metal pattern including a gate electrode overlapping the active pattern, a planarized insulation layer disposed on the gate metal pattern, and a source metal pattern disposed on the planarized insulation layer is also disclosed.