Asymmetric Gate Line Spacing for Display Substrate Parasitic Capacitance
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Solution Overview
Problem
High-resolution display products, such as 8K, suffer from 'Chuck Mura' defects due to fluctuations in exposure critical dimension (CD) during the manufacturing process, leading to uneven parasitic capacitance and brightness issues across pixel regions.
Innovation Solution
The display substrate design includes a base substrate with a gate metal pattern and a first transparent metal pattern, where the gate lines are offset relative to the common electrode patterns, increasing the distance between them in one row and decreasing it in adjacent rows, thereby reducing parasitic capacitance and mitigating 'Chuck Mura' defects without requiring new masks or upgraded equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate line is positioned symmetrically between common electrode patterns in adjacent rows, then the manufacturing process is simple, but the parasitic capacitance fluctuates due to exposure CD variations causing Chuck Mura defects
Solution Approach 1:
The gate line is positioned asymmetrically relative to the common electrode patterns in adjacent rows. Specifically, the distance from the gate line to the common electrode pattern in the first row is different from the distance to the common electrode pattern in the second row. This asymmetric positioning compensates for exposure CD fluctuations, ensuring that parasitic capacitance remains stable even when exposure conditions vary, thereby preventing Chuck Mura defects.
2Area of stationary object
If the distance between gate line and common electrode patterns is reduced, then the pixel area increases, but the parasitic capacitance increases causing brightness uniformity issues
Solution Approach 1:
The patent applies different distances between the gate line and common electrode patterns in different rows. The first row has a larger distance while the second row has a smaller distance. This local differentiation allows the pixel area to be maximized overall while the increased distance in the first row compensates for parasitic capacitance, maintaining brightness uniformity across the display.
3Object-generated harmful factors
If asymmetric positioning of gate line is implemented, then parasitic capacitance is reduced and Chuck Mura defects are minimized, but the manufacturing complexity increases
Solution Approach 1:
The asymmetric positioning of the gate line is predetermined in the mask design phase. By pre-calculating and pre-positioning the gate line at specific asymmetric distances from common electrode patterns in different rows, the compensation for parasitic capacitance is built into the structure itself. This eliminates the need for complex real-time adjustments during manufacturing, reducing actual manufacturing complexity while maintaining the parasitic capacitance reduction benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces parasitic capacitance, minimizes 'Chuck Mura' defects, and improves the yield of high-end display products by adjusting exposure process conditions, enhancing the adaptability of existing exposure machines for high-end and OLED manufacturing.
Implementation Method 1
the fluctuation of an exposure critical dimension (CD) has a greater effect on a parasitic capacitance and the pixels of the product having the resolution of 8K than that of the product having the resolution of 4K
Data Source
AI summary
A display substrate includes a base substrate; a gate metal pattern including a gate electrode of a thin film transistor and gate lines; a source-drain metal pattern including a source electrode and a drain electrode of the thin film transistor, and data lines, where the gate line cross the data line, to define a plurality of pixel regions arranged in an array form; and a first transparent metal pattern including a common electrode pattern. A minimum distance between each gate line and common electrode patterns in a row of pixel regions located in a same row as the gate line in a first direction is a first spacing, a minimum distance between the gate line and common electrode patterns in the other row of pixel regions adjacent to the gate line in the first direction is a second spacing, and the first spacing is greater than the second spacing.