Display Substrate Wiring Layout for Coupling Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional liquid crystal display devices with plane-to-line switching (PLS) mode face issues such as coupling capacitance between the data line and common electrode, leading to signal delay and limitations in increasing lateral visibility and brightness, due to the use of organic insulation layers that can be damaged at high temperatures.
Innovation Solution
The implementation of an improved wiring structure that reduces coupling capacitance between the data line and common electrode by using a gate line, data line, and electrodes, along with a substrate structure that includes a switching device, gate insulation layer, source electrode, drain electrode, and pixel electrode, where the data line is connected to the gate electrode and the pixel electrode is connected to the drain electrode, without an organic insulation layer, thereby preventing signal delay and increasing the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an organic insulation layer is used between the data line and common electrode to reduce coupling capacitance, then coupling capacitance is reduced, but the insulation layer is damaged during high-temperature processes causing additional contacts to be needed
Solution Approach 1:
The patent removes the organic insulation layer from the structure between the data line and common electrode. By extracting this problematic layer, the invention eliminates the damage issue during high-temperature processes while maintaining coupling capacitance reduction through alternative structural design of the wiring layout and spacing.
Solution Approach 2:
The patent changes the structural parameters of the wiring system by adjusting the spacing, positioning, and configuration of the data line and common electrode. This parameter optimization reduces coupling capacitance without requiring the organic insulation layer, thereby avoiding manufacturing issues while achieving the desired electrical isolation.
2Reliability
If a thick organic insulation layer is used to reduce coupling capacitance, then coupling capacitance is reduced, but the aperture ratio is decreased
Solution Approach 1:
The patent extracts and removes the thick organic insulation layer that was occupying space in the pixel structure. This elimination of unnecessary material increases the aperture ratio while the coupling capacitance is controlled through optimized wiring geometry and spacing between conductive elements.
Solution Approach 2:
The patent optimizes the geometric parameters of the data line and common electrode, including their width, spacing, and relative positioning. These parameter changes reduce coupling capacitance through increased separation and optimized layout, eliminating the need for thick insulation layers and thereby increasing the aperture ratio.
3Reliability
If conventional wiring structure is used with organic insulation layer, then coupling capacitance is reduced, but signal delay occurs due to layer damage
Solution Approach 1:
The patent removes the organic insulation layer that causes signal delay through damage during processing. By extracting this problematic component, the invention creates a more reliable electrical connection path that reduces signal delay while maintaining coupling capacitance control through alternative structural means.
Solution Approach 2:
The patent changes the wiring structure parameters by optimizing the configuration, spacing, and material composition of the data line and common electrode. These parameter modifications reduce both coupling capacitance and signal delay by creating a more efficient electrical pathway without the interfering organic insulation layer.
Data Source
AI summary
A display substrate for a display device includes a substrate, a switching device, a gate line, a data line, a pixel electrode, a plurality of common electrodes. The switching device includes an active pattern, a gate insulation layer, a gate electrode, a source electrode and a drain electrode. The gate line is electrically connected to the source electrode, and the data line is electrically coupled to the gate electrode. The pixel electrode is electrically connected to the drain electrode, and the common electrodes are disposed on the pixel electrode. A coupling capacitance among the common electrodes and the data line can be prevented and/or reduced to prevent a signal delay of the data line. Further, an aperture ratio of the display substrate can be improved by changing a layout of the data line and the gate line.