Display Sync Signal Control for Multi-Speed Video Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing synchronization control circuits for flat panel displays face challenges in maintaining video quality due to large frequency differences between input and display vertical synchronization signals, particularly in multiple-speed driving scenarios, leading to image deterioration and synchronization delays.
Innovation Solution
A synchronization signal generating device that measures the vertical synchronization interval of the input video signal, detects phase differences between input and display synchronization signals, and adjusts the cycle of the display vertical synchronization signal within a compensation interval to minimize phase differences, ensuring synchronization in a shorter time while preventing image deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the display vertical synchronization signal is synchronized with the input vertical synchronization signal once the starting position falls within the compensation interval, then the synchronization is maintained thereafter, but large frequency differences between fields cause video quality deterioration
Solution Approach 1:
The patent applies preliminary action by performing phase difference detection and cycle adjustment before the starting position falls within the compensation interval. The phase difference detecting unit detects the phase difference between input and display vertical synchronization signals, and the vertical cycle determining unit determines an adjusted cycle within the compensation interval to decrease the phase difference, proactively preventing synchronization issues before they occur.
Solution Approach 2:
The patent implements feedback through the phase difference detecting unit that continuously monitors the phase difference between input and display vertical synchronization signals. Based on this feedback, the vertical cycle determining unit adjusts the display vertical synchronization cycle to minimize phase differences, creating a closed-loop control system that adapts to frequency variations and maintains video quality.
2Adaptability or versatility
If the frequency difference between input and display vertical synchronization signals is large, then synchronization adjustment is needed, but multiple-speed driving makes the frequency difference noticeable and degrades image quality
Solution Approach 1:
The patent applies dynamics by making the display vertical synchronization cycle adjustable rather than fixed. The vertical cycle determining unit dynamically determines an adjusted cycle within the compensation interval based on the detected phase difference, allowing the system to adapt to varying input frequencies while maintaining synchronization. This dynamic adjustment prevents noticeable frequency differences during multiple-speed driving.
3Speed
If the vertical synchronization interval is adjusted within the compensation interval to decrease phase difference, then synchronization speed increases, but the complexity of cycle determination increases
Solution Approach 1:
The patent applies parameter changes by adjusting the vertical synchronization cycle parameter within the compensation interval. The vertical cycle determining unit changes the cycle parameter based on the phase difference detection results, enabling faster synchronization. The system modifies the cycle length parameter to achieve optimal synchronization speed while managing complexity through structured parameter adjustment.
Data Source
AI summary
According to embodiments, a synchronization signal generating device includes: a cycle measuring unit configured to measure the vertical synchronization interval of the input video signal; a phase difference detecting unit configured to detect a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal; and a vertical cycle determining unit configured to determine a cycle of the display vertical synchronization signal based on a measurement result of the cycle measuring unit and a detection result of the phase difference detecting unit so that the phase difference is decreased within the range of the compensation interval, and to determine 1/n of the cycle of the display vertical synchronization signal as a cycle of an n-times speed vertical synchronization signal.