Display TFT Layout Using Mixed Semiconductors for Mobility Stability
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Solution Overview
Problem
Current display apparatuses face challenges in achieving optimal mobility and stability in thin film transistors, particularly in oxide semiconductor devices, due to variations in oxygen content and process conditions, which affect current drivability and uniformity, especially in large-area applications.
Innovation Solution
A display apparatus design that includes thin film transistors with different semiconductor materials (polysilicon and oxide semiconductor) in display and non-display areas, with varying gate insulating layer thicknesses to manage mobility and stability, allowing for distinct operational characteristics in switching and driving functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If oxide semiconductor thin film transistors are used to achieve high mobility, then electron mobility is improved, but stability is degraded due to resistance variation with oxygen content
Solution Approach 1:
The patent applies local quality by creating distinct gate insulating layer structures for different functional areas: the display area uses a first gate insulating layer with specific thickness optimized for switching transistor performance, while the non-display area uses a second gate insulating layer with different thickness optimized for driving transistor stability. This spatial differentiation allows each region to have tailored electrical characteristics appropriate to its function.
Solution Approach 2:
The patent changes the physical parameter of gate insulating layer thickness to resolve the contradiction. By varying the thickness parameter between different gate insulating layers (first gate insulating layer vs. second gate insulating layer), the patent optimizes mobility in one region while ensuring stability in another, thereby decoupling the trade-off through parameter differentiation.
2Speed
If polycrystalline silicon thin film transistors are used to achieve high electron mobility and stability, then manufacturing complexity increases due to required crystallization processes
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to oxide semiconductor, fundamentally simplifying the manufacturing process. Oxide semiconductors can be deposited and crystallized at lower temperatures without requiring the complex high-temperature crystallization processes needed for polycrystalline silicon, thereby achieving comparable performance with reduced manufacturing complexity.
3Reliability
If varying gate insulating layer thicknesses are used to optimize transistor performance, then manufacturing precision requirements increase
Solution Approach 1:
The patent segments the gate insulating layer into multiple distinct layers (first gate insulating layer and second gate insulating layer) with different thicknesses optimized for different functions. This segmentation allows each layer to be independently optimized and controlled, making the overall thickness variation more manageable and less critical than controlling a single uniform thickness across all transistors.
Data Source
AI summary
A display apparatus includes a first TFT in a display area including a first semiconductor pattern including a polysilicon, a first gate electrode overlapping with the first semiconductor pattern under conditions that a first gate insulating layer is interposed, and first source and drain electrodes connected to the first semiconductor pattern, a second TFT in the display area including a second semiconductor pattern including a first oxide semiconductor, a second gate electrode overlapping with the second semiconductor pattern under conditions that second and third gate insulating layers are interposed, second source and drain electrodes connected to the second semiconductor pattern, and a third TFT in a non-display area including a third semiconductor pattern including a second oxide semiconductor, a third gate electrode overlapping with the third semiconductor pattern under conditions that the third gate insulating layer is interposed, and third source and drain electrodes connected to the third semiconductor pattern.