Display Substrate Via Sizing to Offset Data-Line Voltage Drop
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Solution Overview
Problem
Display substrates for OLED and QLED displays face issues with long-range brightness unevenness due to voltage drops on data and voltage lines, leading to inconsistent display brightness across the panel.
Innovation Solution
The display substrate design includes pixel driving circuits with transistors and vias that gradually change sizes in specific directions to mitigate voltage drops, ensuring consistent signal transmission and improved brightness uniformity across the display panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data lines and voltage lines are extended across the display panel to reach all pixel circuits, then all pixels can be electrically connected and controlled, but voltage drops occur along the lines causing long-range brightness unevenness
Solution Approach 1:
The patent applies local quality by making via sizes non-uniform across the display panel. Specifically, via sizes connected to data lines and voltage lines are designed to gradually increase from the signal input end toward the distal end, compensating for voltage drops in different regions. This local variation in via dimensions optimizes electrical connection quality at each specific location rather than using a uniform via size throughout the panel.
2Ease of manufacture
If uniform via sizes are used throughout the display panel, then manufacturing is simplified, but voltage drops cause brightness inconsistency across different regions
Solution Approach 1:
The patent implements local quality by designing different via sizes for different regions of the display panel. Vias connected to data lines and voltage lines have sizes that gradually increase from the signal input end to the distal end, creating a non-uniform via size distribution that compensates for voltage drops in different regions while maintaining manufacturing feasibility through systematic size progression.
Data Source
AI summary
A display substrate includes a plurality of data lines and a plurality of columns of pixel driving circuits. A column of pixel driving circuits is connected to a corresponding data line, and each pixel driving circuit includes a driving transistor and a first transistor. The driving transistor is a P-type transistor. The first transistor includes: a first active pattern having a first channel region, and a first doped region and a second doped region on two opposite sides of the first channel region; a first gate; and a first insulating block disposed on a side of the first active pattern away from the base and having a first via. The data line is connected to a portion of the first active pattern located in the first doped region through the first via. Sizes of all first vias in the column of pixel driving circuits gradually decrease in a first direction.