Semiconductor Display Wiring Structure for Luminance Uniformity
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Solution Overview
Problem
High-definition semiconductor display devices using light-emitting elements face issues with luminance unevenness due to potential drops in wiring resistance, particularly as the number of pixels increases, making it difficult to control switching transistors and maintain image quality.
Innovation Solution
The solution involves electrically connecting power supply lines through auxiliary power supply lines and forming auxiliary wirings over an interlayer insulating film to reduce combined resistance and prevent potential drops, allowing for effective control of switching transistors and maintaining image quality across a large display region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of pixels is increased to achieve higher definition, then the image quality is improved, but the potential drop of scan lines increases due to increased resistance
Solution Approach 1:
The patent introduces auxiliary scan lines formed in a different layer (second conductive layer) above the interlayer insulating film, creating a three-dimensional wiring structure. This allows the auxiliary scan lines to be electrically connected to the main scan lines through contact holes, providing an additional dimensional path for signal transmission that reduces the effective resistance and potential drop in the horizontal direction.
Solution Approach 2:
The auxiliary scan lines act as intermediary conductors between the main scan lines and the gate electrodes. By forming these auxiliary lines in a separate layer and connecting them through contact holes, the patent creates an intermediate transmission path that reduces the overall resistance and potential drop affecting the gate control signals.
2Reliability
If materials with lower resistivity are used for scan lines, then potential drop is suppressed, but material selection is limited due to heat resistance requirements for gate electrodes
Solution Approach 1:
The patent divides the scan line function into two separate segments: main scan lines formed in the first conductive layer that require high heat resistance for gate electrode formation, and auxiliary scan lines formed in the second conductive layer that can use materials with lower resistivity. This segmentation allows each segment to be optimized for its specific function without compromising the other.
Solution Approach 2:
The patent applies different material qualities to different parts of the wiring system. The main scan lines use materials with high heat resistance (such as aluminum or copper alloys) suitable for gate electrode formation, while the auxiliary scan lines use materials with lower resistivity (such as copper or tungsten) optimized for signal transmission. Each layer has locally optimized material properties according to its specific functional requirements.
3Area of stationary object
If power supply lines are extended to cover large display regions, then current supply is improved, but luminance unevenness occurs due to potential drops
Solution Approach 1:
The patent introduces auxiliary power supply lines formed in a second conductive layer above the interlayer insulating film, creating a vertical stacking structure. These auxiliary power supply lines are electrically connected to the main power supply lines through contact holes, providing an additional dimensional path for current transmission that reduces the effective resistance and potential drop across large display regions.
Solution Approach 2:
The auxiliary power supply lines serve as intermediary conductors that reduce the overall resistance between the power supply source and the light-emitting elements across large display regions. By forming these auxiliary lines in a separate layer and connecting them through contact holes, the patent creates an intermediate current transmission path that maintains more uniform potential distribution.
Data Source
AI summary
A semiconductor display device using a light-emitting element, which can suppress luminance unevenness among pixels due to the potential drop of a wiring, is provided. Power supply lines to which a power supply potential is supplied are electrically connected to each other in a display region where a plurality of pixels are arranged. Further, an interlayer insulating film is formed over a wiring (an auxiliary power supply line) for electrically connecting the power supply lines to each other in the display region and a gate electrode of a transistor included in a pixel; and the power supply lines are formed over the interlayer insulating film which is formed over the auxiliary power supply line and the gate electrode. Furthermore, a wiring (an auxiliary wiring) formed over the interlayer insulating film is electrically or directly connected to the auxiliary power supply line.