Distributed Calibration Data Storage for High-Speed Device Testing
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Solution Overview
Problem
Current device testing systems face challenges in efficiently managing and storing calibration data, particularly with the increasing complexity of System on a Chip (SOC) devices, where escalating test data volumes and high-speed interfaces require improved data storage and processing to ensure quality and reliability, while conventional calibration data only includes propagation delay information, neglecting frequency characteristics.
Innovation Solution
The proposed solution involves storing calibration data in non-volatile memory across multiple components of the test system, including channel modules and device interfaces, using compensation filters and frequency characteristics to enhance data transmission, with encryption options for security, allowing for efficient data management and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If calibration data is stored only in central memory, then system simplicity is maintained, but data access efficiency and reliability deteriorate
Solution Approach 1:
The patent divides calibration data into multiple segments and stores them in different memory locations: channel module memory (first memory), device interface memory (second memory), and central memory (third memory). This segmentation allows parallel access to different calibration parameters, improving data access efficiency while maintaining system modularity.
Solution Approach 2:
The patent introduces a spatial dimension to calibration data storage by distributing data across multiple memory hierarchies (channel level, interface level, and central level). This multi-dimensional storage architecture enables simultaneous access from different levels, resolving the trade-off between simplicity and access efficiency.
2Quantity of substance
If conventional calibration data storage is used, then storage capacity is sufficient for simple tests, but data capacity becomes insufficient for complex SOC testing
Solution Approach 1:
The patent segments calibration data into different categories and storage locations: propagation delay data in channel module memory, frequency characteristic data in device interface memory, and comprehensive calibration data in central memory. This segmentation enables the system to handle complex SOC testing requirements by accessing appropriate data from appropriate memory levels.
Solution Approach 2:
The multi-level memory architecture serves multiple functions: fast access to critical calibration parameters, reliable storage of comprehensive data, and adaptive support for different test complexities. The system can selectively use data from different memory levels based on testing requirements.
3Reliability
If calibration data is stored in distributed memory, then data access reliability is improved, but system complexity increases
Solution Approach 1:
The patent implements a segmented memory architecture where each segment (channel module memory, device interface memory, central memory) has a specific role. This segmentation improves reliability through redundancy and distributed access while managing complexity through clear functional separation of memory segments.
4Loss of time
If only propagation delay calibration is performed, then calibration speed is fast, but test quality deteriorates due to lack of frequency characteristics
Solution Approach 1:
The patent performs comprehensive calibration including frequency characteristic measurements in advance and stores the results in distributed memory. During actual testing, the pre-calculated frequency compensation data is quickly retrieved and applied, achieving both high test quality and fast calibration speed through preliminary preparation.
Data Source
AI summary
Embodiments of the present invention provide systems and methods for storing calibration data for a test system operable to test a device under test (DUT). The test system includes one or more channel modules and a device interface. A first part of the calibration data is stored on a non-volatile memory. The non-volatile memory can be disposed in different parts of the test system. The non-volatile memory is located on the device interface and can also be located on one or more of the channel modules, as well as an attachment of the test system. The non-volatile memory is associated with the one or more channel modules. The second part of the calibration data is stored on a non-volatile memory associated with the device-under-test interface.