Distributed Clock Signal Generator for IC Noise Reduction
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Solution Overview
Problem
Increasing clock frequency in integrated circuits leads to noise interference and requires extensive shielding and correction measures, which increase complexity and power consumption, making it costly and inefficient to distribute high-frequency clock signals effectively.
Innovation Solution
A distributed clock signal generator using a primary oscillator and secondary oscillators with frequency correction units to adjust the reference control signal, allowing the duplication of the primary clock signal without duplicating the complete PLL, thereby reducing complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency of the integrated circuit is increased to provide more computing power, then the computing power is improved, but extensive shielding and correction measures are required which increase device complexity and power consumption
Solution Approach 1:
The patent divides the clock distribution system into multiple independent clock domains, each with its own PLL and clock buffer. This segmentation allows each domain to operate independently at optimal frequencies without requiring extensive shielding across the entire chip, thereby reducing overall device complexity while maintaining high computing power.
Solution Approach 2:
The patent implements local clock generation by placing PLLs near specific logic units that require high-frequency operation. This local quality approach ensures that shielding and correction measures are only applied where high-frequency clocks are actually needed, rather than across the entire integrated circuit, thus reducing overall complexity.
2Reliability
If extensive shielding and correction measures are provided to guarantee failure-free transmission of high frequency clock signal, then the reliability is improved, but the device complexity increases
Solution Approach 1:
By segmenting the clock distribution into multiple independent domains with separate PLLs and buffers, the patent isolates potential interference and noise in each domain. This segmentation maintains reliable clock transmission within each domain without requiring extensive cross-domain shielding, thereby reducing overall device complexity.
Solution Approach 2:
The patent introduces clock buffers as intermediary elements between the PLLs and the logic units. These buffers act as mediators that isolate the clock signal paths, ensuring clean transmission without requiring extensive shielding infrastructure, thus maintaining reliability while reducing complexity.
3Device complexity
If local PLLs are placed near single logic units to avoid shielding measures, then the shielding requirements are reduced, but the power consumption increases and significant chip area is required
Solution Approach 1:
The patent applies local quality by placing PLLs only near logic units that require high-frequency operation, rather than uniformly across the entire chip. This selective local placement reduces the number of PLLs needed compared to a fully distributed approach, thereby reducing power consumption while still minimizing shielding requirements in critical areas.
4Device complexity
If redundant duplicate PLL circuits are added near each logic unit to avoid shielding, then the shielding measures are reduced, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements local quality by strategically placing PLLs only where high-frequency clock generation is actually needed, rather than duplicating PLLs at every logic unit. This selective approach reduces the total number of PLLs required, thereby lowering manufacturing complexity and cost while still achieving the goal of reduced shielding requirements.
Data Source
AI summary
The present invention provides a clock source for an integrated circuit, comprising a primary oscillator adapted to generate a primary clock signal based on a reference control signal, at least one secondary oscillator each secondary oscillator being adapted to generate a secondary clock signal based on the reference control signal, wherein for each secondary oscillator a frequency correction unit is provided and adapted to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal. The present invention furthermore provides a method for providing a clock signal, and an integrated circuit.