Signal-duration filters and timers detect PLL synchronization while reducing semiconductor die area and power consumption.
Integrated USB PHY regulation circuit supplies 3.3V from bus voltage, eliminating external power sources and reducing implementation costs.
Segmented LC resonators with varied bond wires resolve the contradiction between frequency selectivity and bandwidth in RF transistor amplifiers.
Series resistors in the differential amplifier extend the linear region, preventing phase noise deterioration and deadlock states.
Measuring radio wave air travel time between the base station and mobile device prevents relay attacks by enforcing a strict maximum distance limit.
A reset circuit uses a starter mechanism to generate accurate power-on signals for semiconductor devices.
A level shifting circuit converts symmetrical input signals into asymmetrical output voltages to drive silicon carbide MOSFET gates.
A distributed clock signal generator uses frequency correction units to duplicate primary clock signals across secondary oscillators.
A fractional-N synthesizer initializes interpolators via a timeout circuit to resolve long synchronization times and noise degradation.
Segmenting frequency control into independent open-loop and closed-loop paths stabilizes steady-state frequency without compromising transient response speed.
Integrated silicon photonics control module manages signal processing and modulation formats on a single substrate.
A dual-oscillator system uses periodic high-accuracy calibration to maintain precise timekeeping.
Segmented feedback loops isolate noise sources in a frequency generator, reducing phase jitter and improving response speed.
A phase-locked loop uses a state machine to select phase-shifted clocks, producing low phase-noise oscillations.
Replacing continuous-time amplifiers with switched-capacitor feedback reduces noise and power consumption while maintaining precise common-mode voltage control.
A film substrate antenna generates a counteracting electromagnetic wave to reduce interference in semiconductor packages.
A built-in self-test circuit measures phase jitter using a variable Vernier digital delay locked line, resolving high-speed measurement complexity.
A variable frequency circuit adjusts oscillator output using dithering sequences to spread spurious tones across the spectrum.
Automatic phase-locking eliminates manual current balancing and cross-talk, reducing energy loss while maintaining high power delivery.