Fractional-N Synthesizer Phase Synchronization via Timeout Circuit
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Solution Overview
Problem
Fractional-N synthesizers face challenges in synchronizing output phase and frequency, particularly when M is large, leading to long synchronization times, increased power consumption, and noise degradation, especially when multiple synthesizers require consistent phase relationships with each other rather than the reference.
Innovation Solution
A fractional-N synthesizer system where multiple synthesizers are updated simultaneously to generate the same output frequency, using a phase locked loop with a frequency divider and interpolator, and a timeout circuit to initialize the interpolator to the same start condition, allowing synchronization without continuous clocking and reducing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronization pulses are provided every K cycles with respect to fref where K is a multiple of M, then the output phase can be synchronized with the reference, but the time interval between synchronization pulses becomes very long when M is large
Solution Approach 1:
The patent introduces an intermediary synchronization signal that is generated independently of the reference frequency divider chain. This intermediary signal directly triggers the interpolator reset without requiring waiting for the long K-cycle reference period, thus mediating between the need for phase synchronization and the requirement for fast settling time.
Solution Approach 2:
The synchronization mechanism is prepared in advance by having a dedicated synchronization input that can immediately reset the interpolator when needed, rather than waiting for the periodic reference-based synchronization opportunity. This preliminary preparation of the synchronization path enables immediate phase alignment when frequency changes occur.
2Reliability
If a divide-by-K synchronization counter is continuously clocked by the reference to provide synchronization pulses, then phase synchronization is maintained, but power consumption increases and switching noise degrades phase noise performance
Solution Approach 1:
Instead of continuously clocking the synchronization counter at every reference cycle, the patent uses periodic synchronization only when frequency changes occur. The synthesizer detects frequency updates and triggers interpolator reset only at those moments, converting continuous periodic action into event-driven periodic action that consumes power only when necessary.
Solution Approach 2:
The synthesizer monitors its own frequency update events and automatically triggers the appropriate synchronization action without requiring an external continuous synchronization counter. The system serves its own synchronization needs by detecting when frequency changes occur and autonomously resetting the interpolator at those moments.
3Reliability
If continuous clocking is used to maintain synchronization, then phase consistency is maintained, but switching noise causes spurious sidebands at offsets of +/−fref/K around the output carrier frequency
Solution Approach 1:
The patent extracts the essential synchronization function from the continuous reference clocking mechanism. By removing the continuous counter operation and keeping only the critical reset function triggered by frequency updates, it eliminates the source of switching noise while preserving the necessary phase consistency through selective interpolator initialization.
4Adaptability or versatility
If the interpolator state varies depending on the particular state when new N and F values are loaded, then frequency switching is flexible, but the output phase relationship with reference becomes inconsistent
Solution Approach 1:
The patent applies preliminary action by resetting the interpolator to a known initial state immediately when frequency updates occur. This preliminary reset ensures that regardless of the previous interpolator state, the phase relationship is consistently established from a known starting point, combining the flexibility of frequency switching with consistent phase relationships.
Data Source
AI summary
A fractional-N synthesizer system including a plurality of fractional-N synthesizers all updated to simultaneously generate an output frequency from the same reference frequency, a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency; the phase locked loop including a frequency divider, an interpolator responsive to an input fraction to provide to the frequency divider an output which has a fractional value equal to on average, the input fraction; and a timeout circuit responsive to the reference frequency for generating an output a predetermined time after updating to initialize the interpolator in each synthesizer to the same start conditions for locking together the phase of the frequency outputs of all of the synthesizers at the updated frequency.