PLL Non-Integer Divider for Low Phase Noise Clock Recovery
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Solution Overview
Problem
High-speed communication systems face challenges in achieving low phase noise and high data rate transmission due to limitations in integrated circuit manufacturing and conflicting design goals for multiple protocols, which restrict the performance of transceiver devices.
Innovation Solution
A phase-locked loop (PLL) circuit with a non-integer divider is implemented, using a voltage-controlled oscillator (VCO) to produce phase-shifted clocks and a state machine to dynamically select new clocks based on phase differences, allowing for low phase-noise oscillations and adaptable frequency division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher clock speeds are used to achieve high data rate transmission, then data throughput increases, but phase noise increases and clock jitter degrades
Solution Approach 1:
The patent implements a dynamic frequency synthesis system using a phase-locked loop that can adaptively adjust the output frequency and phase based on feedback. The VCO frequency is dynamically controlled by the phase detector output, allowing the system to maintain optimal performance across varying data rates while minimizing phase noise through active feedback correction.
Solution Approach 2:
The patent employs a phase-locked loop feedback mechanism where the phase detector continuously compares the reference signal with the divided feedback signal and generates an error signal to adjust the VCO frequency. This closed-loop feedback system actively compensates for phase noise and jitter, maintaining low phase noise performance even at high clock speeds required for high data throughput.
2Measurement precision
If precise signal alignment is required for clock recovery, then clock recovery accuracy improves, but bandwidth requirements increase and system complexity increases
Solution Approach 1:
The patent implements a universal phase-locked loop circuit that can operate across multiple data rate standards and protocols. The same core circuitry (VCO, phase detector, charge pump, feedback divider) serves multiple functions by adjusting division ratios and frequency settings, eliminating the need for separate clock recovery circuits for different standards and reducing overall system complexity while maintaining high clock recovery accuracy.
Solution Approach 2:
The patent utilizes programmable division ratios and adjustable VCO frequency ranges to adapt the clock recovery circuit to different data rate requirements. By changing the division ratio N and reference frequency, the same hardware can achieve precise clock recovery for various serial data rates without increasing system complexity, as the parameters are software-configurable rather than requiring hardware changes.
3Speed
If alternate integrated circuit fabrication processes (silicon germanium or gallium arsenide) are used to achieve greater speeds, then operating speed increases, but manufacturing costs increase substantially
Solution Approach 1:
The patent achieves high operating speeds in standard CMOS technology by optimizing circuit parameters including minimizing the VCO period, using high-gain phase detectors, implementing efficient charge pump design, and optimizing the feedback division ratio. These parameter optimizations allow the PLL to lock quickly and operate at high frequencies without requiring expensive alternative semiconductor materials, maintaining cost-effectiveness while achieving the required speed performance.
Data Source
AI summary
A phase-locked loop with a non-integer divider utilizes a state machine to periodically select a new clock from a plurality of clocks for comparison to a reference signal after division by an integer divide by N block. Based on a desired divider ratio, the state machine selects the new clock that is phase shifted with respect to a presently selected clock. Each change from the presently selected clock to the new clock produces a selected clock cycle that is expanded or contracted by the amount of phase shift between the new clock and the presently selected clock. The integer divide by N block divides the selected clock by the integer portion of the desired divider ratio producing a divided clock that is effectively divided by a non-integer amount.