Variable Vernier Digital Delay Locked Line Jitter Measurement
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Solution Overview
Problem
Current methods for measuring jitter in phase-locked loops (PLLs) are inadequate for high-volume production, as they lack accurate mechanisms to assess jitter in high-speed digital circuitry, leading to potential shipment of PLLs that do not meet design specifications.
Innovation Solution
A built-in self-test (BIST) circuit utilizing a Variable Vernier Digital Delay Locked Line method, incorporating a digital delay locked loop and a Vernier delay line for coarse and fine tuning, respectively, to accurately measure phase and cycle-to-cycle jitter over a wide input frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional jitter measurement methods are used, then measurement capability is limited, but implementation complexity and cost are reduced
Solution Approach 1:
The BIST circuit enables the PLL to self-test its own jitter performance by incorporating measurement functionality directly into the PLL structure. The phase detector, delay elements, and counters work together to automatically measure and report jitter without requiring external measurement equipment, thus achieving high measurement precision while maintaining relatively simple implementation
Solution Approach 2:
The measurement circuit components serve multiple functions: the phase detector is used both for PLL operation and for jitter measurement, the delay elements are used for both signal processing and time interval measurement, and the counters serve both control and measurement purposes. This multi-functionality reduces overall circuit complexity while enabling accurate jitter measurement
2Speed
If high-speed digital circuitry is used, then performance increases, but jitter becomes a more critical and difficult to measure parameter
Solution Approach 1:
The patent replaces traditional analog jitter measurement methods with a digital measurement approach. By using digital delay elements and counters to measure phase differences, the system achieves picosecond-level measurement precision necessary for high-speed clock signals, where analog methods would be insufficient due to noise and bandwidth limitations
Solution Approach 2:
The patent transforms the time-domain jitter measurement problem into a spatial-domain measurement by using parallel delay paths with different delay values. The phase detector compares signals that have traversed different spatial paths, converting temporal phase differences into detectable voltage differences that can be measured with high precision
3Measurement precision
If built-in self-test circuit is implemented, then measurement accuracy improves, but area overhead increases
Solution Approach 1:
The BIST circuit reuses existing PLL components for measurement purposes: the phase detector serves both PLL locking and phase difference measurement, the delay elements are used for both signal timing and measurement intervals, and the counters serve both control sequencing and jitter value measurement. This eliminates the need for separate dedicated measurement hardware, significantly reducing area overhead while maintaining high measurement accuracy
Solution Approach 2:
The patent merges the jitter measurement functionality with the PLL operational components. The measurement function is integrated into the existing signal path rather than being added as a separate parallel system. By combining measurement functions with operational functions in the same hardware blocks, the circuit achieves accurate jitter measurement with minimal additional area
Data Source
AI summary
An improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal, the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.