Reset Circuit Power-On Detection Reliability
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Solution Overview
Problem
Existing reset circuits in semiconductor devices face issues with power-on and power-down detection due to slow voltage increases or voltage swings, leading to incomplete initialization of internal circuits and potential reliability failures from capacitor degradation, especially in hot-swap scenarios.
Innovation Solution
A reset circuit design incorporating power-on and power-down detection circuits with clamping switches and leak prevention mechanisms to ensure accurate signal generation and reduce capacitor degradation, utilizing a starter circuit with a cut-off switch to prevent capacitor charging during power-on, thereby maintaining the capacitor's reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional detection circuit with a transistor and load circuit is used to detect power-on, then the circuit can generate a power-on detection signal, but when the power supply voltage increases slowly or swings, the dividing circuit cannot output a normal voltage, causing the drain node to change to ground voltage prematurely and preventing proper reset
Solution Approach 1:
The starter circuit activates before the main detection circuit to pre-charge the drain node to a high level. This preliminary action ensures that even if the power supply voltage increases slowly or swings, the drain node maintains its high level until the power-on detection signal is properly generated, preventing premature transition to ground voltage and ensuring reliable reset detection
Solution Approach 2:
The starter circuit acts as an intermediary between the power supply and the main detection circuit. It provides a temporary charging path through the start transistor and capacitor to establish proper initial conditions for the detection circuit, bridging the gap during power-on transitions when the main detection circuit might otherwise fail to operate correctly
2Reliability
If a capacitor is used in the starter circuit to initialize the detection circuit at power-on, then the detection circuit can be properly initialized, but the capacitor degrades due to TDDB (Time-Dependent Dielectric-Breakdown) from continuous voltage application, causing leak current and reset circuit failure
Solution Approach 1:
The cut-off switch periodically disconnects the capacitor from the power supply voltage during normal operation, allowing the capacitor to rest and reducing cumulative stress. The capacitor is only connected during power-on initialization and power-down detection periods, creating a periodic on-off pattern that significantly reduces TDDB degradation and extends capacitor lifespan while maintaining its initialization function
Solution Approach 2:
The cut-off switch extracts the capacitor from the continuous voltage application path during normal operation. By removing the capacitor from the circuit when not needed for initialization or detection, the harmful voltage stress is eliminated, preventing leak current development and extending the capacitor's operational life
3Reliability
If the power-down detection circuit continuously monitors power supply voltage, then power-down can be detected, but the dividing circuit consumes excessive current when operating in linear region during normal power-on state
Solution Approach 1:
The power-down detection circuit dynamically switches between different operating modes using control transistors. During normal power-on state, the circuit transitions to a high-impedance state where the dividing circuit operates in saturation region with minimal current consumption. When power-down occurs, the circuit dynamically switches back to linear region operation to detect the voltage drop, achieving both low power consumption and reliable detection
Solution Approach 2:
The circuit changes its operating parameters by switching transistors between saturation and linear regions. During normal operation, parameter changes place the dividing circuit in saturation mode with high output impedance, minimizing current draw. Upon power-down detection, parameters are changed to allow linear region operation for accurate voltage monitoring, optimizing both energy efficiency and detection capability
Data Source
AI summary
In a power-on detection circuit, a first connection node at which a first divided voltage is generated is connected to a second power supply line during activation of a power-down detection signal. Inactivation timing of the power-down detection signal is set earlier than an activation timing of a power-on detection signal. Therefore, the first transistor whose gate is connected to the first connection node is certainly turned off in the first half of a power-on period, which prevents the power-on detection signal from being activated during the power-on period. Further, a leak current flowing through the first transistor is reduced. In the second half of the power-on period, the power-on detection signal is certainly generated using the first divided voltage generated by the first dividing circuit. Thus, operating a reset circuit without malfunction and normally outputting a reset signal is possible disregarding behavior of a power supply voltage at power-on.