Level Shifting Circuit for SiC MOSFET Asymmetric Gate Drive
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional symmetric driving circuits are unable to efficiently drive silicon carbide (SiC) MOSFETs due to their asymmetric absolute maximum rating (AMR) requirements, as they cannot produce the necessary asymmetrical gate voltages for optimal performance and reliability.
Innovation Solution
A level shifting circuit that includes a capacitor, a voltage divider, and a zener diode to convert symmetrical input signals into asymmetrical output signals suitable for SiC MOSFETs, with optional gate clamping circuits to ensure compliance with the AMR during startup.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional symmetric driving circuit is used, then the circuit structure is simple, but the gate drive signal cannot meet the asymmetric AMR requirements of SiC MOSFET
Solution Approach 1:
The patent applies asymmetry by transforming a symmetric input signal into an asymmetric output signal that matches the SiC MOSFET's asymmetric AMR requirements. The level shifting circuit uses a voltage divider with different resistance values (R1 and R2) to create asymmetric voltage levels, where the positive voltage swing differs from the negative voltage swing, directly addressing the non-symmetric Vgs-on and Vgs-off requirements
Solution Approach 2:
The patent introduces a level shifting circuit as an intermediary component between the symmetric driver and the SiC MOSFET gate. This intermediary circuit includes a capacitor coupled to the gate and a voltage divider network that mediates the signal transformation, converting the symmetric drive signal into the required asymmetric gate voltage while protecting the MOSFET from excessive voltage
2Productivity
If a symmetric drive signal is applied, then the driving circuit operates within its voltage limits, but the SiC MOSFET cannot achieve optimal switching performance
Solution Approach 1:
The patent changes the voltage parameters of the gate drive signal to optimize SiC MOSFET performance. By adjusting the asymmetric voltage levels through the level shifting circuit, the gate voltage can reach optimal values for turn-on and turn-off, enabling higher switching frequencies and reducing both conduction and switching losses. The circuit dynamically adjusts the gate voltage parameters rather than using fixed symmetric levels
3Speed
If the gate voltage is increased to improve switching performance, then switching speed increases, but the voltage may exceed the SiC MOSFET's maximum rating
Solution Approach 1:
The patent implements preliminary action by pre-charging the capacitor coupled to the SiC MOSFET gate before the main switching event. This pre-charging through the voltage divider network ensures that when the gate is activated, the voltage rises to the optimal level without exceeding the maximum rating, thereby achieving fast switching speeds while maintaining reliability and compliance with AMR specifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The level shifting circuit effectively drives SiC MOSFETs within their AMR, reducing conduction and switching losses, and is cost-effective with reduced power losses compared to prior art, while ensuring the gate drive signals remain within the transistor's operational limits.
Implementation Method 1
a capacitor coupled between the input and the output
Implementation Method 2
a voltage divider circuit coupled between the input and a reference node configured to be coupled to a source terminal of the SiC MOSFET
Implementation Method 3
a first diode having an anode coupled to the tap node and a cathode coupled to a terminal of the capacitor
Data Source
AI summary
A level shifting circuit has an input configured to receive an input signal, wherein the input signal has symmetrical maximum and minimum voltages. The level shifting circuit further includes an output configured to provide an output signal, wherein the output signal has asymmetrical maximum and minimum voltages. The output signal is generated in response to the input signal. The output signal is applied to drive a gate terminal of a SiC MOSFET.