Distributed On-Chip Debug Triggering for Low Latency
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Solution Overview
Problem
Conventional processor-based systems face challenges in debugging due to limited data bandwidth and resource constraints of centralized debug state machines, leading to high trigger-to-action latency and difficulty in addressing critical debugging issues.
Innovation Solution
Implementing a distributed on-chip debug triggering system where nodes monitor local buses and communicate trigger events to a centralized debugging state machine using a subset of lines on a global debug bus, allowing for local data collection and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a centralized debug state machine is used to monitor all bus lines, then debugging coverage is comprehensive, but data bandwidth limitations and resource constraints increase trigger-to-action latency
Solution Approach 1:
The patent divides the centralized debugging system into distributed components by placing debug triggering logic at multiple nodes throughout the system. Each node independently monitors its local bus lines and generates triggers locally, segmenting the monolithic centralized approach into parallel distributed units that reduce latency while maintaining comprehensive coverage.
Solution Approach 2:
The patent adds a spatial dimension to the debugging architecture by distributing debug state machines across multiple physical locations rather than concentrating them in a single centralized unit. This dimensional transformation allows parallel processing of debug events across different spatial locations, reducing the time required for trigger detection and response.
2Device complexity
If a centralized debug state machine is used, then resource management is simplified, but the limited resources restrict the flexibility and number of triggers that can be detected
Solution Approach 1:
The patent segments the debugging resources into multiple distributed state machines, each capable of independent operation. This segmentation allows the system to detect and respond to more triggers simultaneously by distributing the detection workload across multiple units, thereby increasing versatility without proportionally increasing overall system complexity.
Solution Approach 2:
Each distributed node in the patent performs self-service by autonomously monitoring its local bus lines, detecting triggers, and generating debug events without requiring constant centralized coordination. This self-service capability increases debugging flexibility and adaptability while keeping resource management complexity manageable through standardized interfaces.
3Measurement precision
If conventional logic analyzer techniques are used to tap signals, then signal analysis is possible, but the process is difficult and ineffective for reconstructing past errors
Solution Approach 1:
The patent implements preliminary action by embedding debug monitoring logic directly into the system nodes before errors occur. This allows the system to continuously capture and record bus line states and trigger events as they happen, making error reconstruction straightforward by simply retrieving pre-captured data rather than attempting to replay complex signal sequences afterward.
Solution Approach 2:
The patent introduces intermediary debug state machines at each node that act as mediators between the bus lines and the analysis tools. These intermediaries capture, buffer, and organize signal data in a structured manner, making it significantly easier to analyze and reconstruct errors compared to directly tapping raw signals with external logic analyzers.
Data Source
AI summary
A method and apparatus for distributed on-chip debug triggering is presented. A first bus includes a plurality of lines and a debugging state machine configurable to monitor the plurality of lines of the first bus. One or more nodes are configurable to detect triggering events and provide, in response to detecting one or more triggering events, signals to the debugging state machine using a first subset of the plurality of lines that is allocated to the node(s).