Distributed Instruction Set Architecture with Dual Execution Pipelines

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Solution Overview

Problem

Existing graphics processing units face a trade-off between processing performance and power efficiency, as the number of specialized elements required for optimal performance leads to increased power usage and area, while a smaller number of generalized elements improves efficiency but delays occur due to scheduling conflicts and the burden of less commonly performed instructions.

Innovation Solution

A distributed instruction set architecture is implemented with primary and secondary execution pipelines, where the primary pipeline is optimized for frequently issued instructions to minimize power usage and area, and the secondary pipeline supports less frequently issued instructions, allowing for parallel execution and redundant data paths to mitigate delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a wide array of specialized elements is used to maximize performance, then processing speed is improved, but power consumption and area increase

Engineering Contradiction:

Improveprocessing speedVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements execution elements that can dynamically perform multiple instruction types rather than being dedicated to a single function. The FFMA elements can execute both FFMA instructions and other instructions (such as FADD, FSUB, FMUL) by reconfiguring their operational mode, thereby reducing the total number of specialized elements needed while maintaining high processing capability for dominant instruction types

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The execution elements are designed to be dynamically reconfigurable between different operational modes. The system can adapt the functionality of execution elements based on the incoming instruction type, allowing the same hardware resource to serve multiple purposes at different times, thus improving both performance and power efficiency

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If a small array of generalized elements is used to reduce area and power, then power efficiency is improved, but processing performance decreases due to scheduling conflicts

Engineering Contradiction:

Improvepower efficiencyVSAvoidprocessing performance

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent applies different levels of specialization to different execution elements based on local requirements. While execution elements are generalized to handle multiple instruction types, they are optimized with specific capabilities for dominant instruction types like FFMA. This local optimization allows the system to achieve high performance for frequently executed instructions while maintaining power efficiency through resource sharing

Inventive Principle:

Principle #3Local quality

3Productivity

If specialized elements are used to optimize dominant instructions, then performance is improved, but area and power overhead increase

Engineering Contradiction:

ImproveperformanceVSAvoidarea

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The execution elements are designed as universal units that can perform multiple instruction types including FFMA, FADD, FSUB, and FMUL. By making execution elements multi-functional, the patent reduces the total number of specialized elements required, thereby decreasing area overhead while maintaining optimization for dominant instruction types through dynamic reconfiguration

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Area of stationary object

If generalized elements are used to reduce area, then area is reduced, but delays occur due to scheduling conflicts

Engineering Contradiction:

ImproveareaVSAvoidexecution delay

Core Design Contradiction:

Area of stationary objectVSLoss of time

Solution Approach 1:

The system performs preliminary classification and routing of instructions to appropriate execution elements before execution begins. By pre-identifying the instruction type and selecting the most suitable execution element in advance, the system minimizes scheduling conflicts and execution delays while maintaining a compact architecture with generalized elements

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10503513B2Dispatching a stored instruction in response to determining that a received instruction is of a same instruction type

Publication Date: 2019.12.10 NVIDIA CORP

AI summary

A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of instructions in the distributed instruction set architecture that are issued frequently. The secondary execution pipeline supports the execution of another subset of instructions in the distributed instruction set architecture that are issued less frequently. Both execution pipelines also support the execution of FFMA instructions as well as a common subset of instructions in the distributed instruction set architecture. When dispatching a requested instruction, an instruction scheduling unit is configured to select between the two execution pipelines based on various criteria. Those criteria may include power efficiency with which the instruction can be executed and availability of execution units to support execution of the instruction.