Distributed JTAG Test Bus Controller Architecture for Parallel Programming
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Solution Overview
Problem
As server complexity increases, traditional JTAG-based on-board scan programming (OSP) faces challenges with long daisy chains, leading to timing issues and slow clock speeds, making it difficult to efficiently program multiple programmable elements in serial operations, which becomes impractical for enterprise servers.
Innovation Solution
A distributed JTAG test bus controller (TBC) architecture is implemented, where multiple TBCs are used, each controlling a single circuit board, allowing for parallel programming and higher clock speeds by confining TAP chains to individual boards and using encoded JTAG commands for efficient control signal and data distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single TBC is used with long daisy chains to control multiple circuit boards, then device complexity is reduced, but timing issues arise and clock speeds must be slowed
Solution Approach 1:
The patent divides the single TBC into multiple distributed TBCs, each responsible for controlling TAP chains on specific circuit boards. This segmentation allows each TBC to manage shorter TAP chains locally, eliminating the timing issues associated with long daisy chains while maintaining manageable system complexity through modular distribution.
2Device complexity
If a single TBC is used for serial operation, then device complexity is reduced, but programming time becomes unacceptable
Solution Approach 1:
The patent segments the programming function across multiple TBCs, each handling programming operations on specific circuit boards independently. This enables parallel programming operations across different boards simultaneously, dramatically reducing total programming time compared to sequential operation while maintaining manageable complexity through distributed architecture.
Solution Approach 2:
The patent transitions from serial time-based programming to parallel space-based programming by distributing TBCs across multiple circuit boards. This dimensional shift from sequential to parallel operation enables simultaneous programming of multiple boards, transforming the programming process from a time-consuming sequential task to an efficient parallel operation.
3Device complexity
If TAP chains span multiple circuit boards, then device complexity is reduced, but timing issues and slow clock speeds occur
Solution Approach 1:
The patent segments long TAP chains into shorter local chains confined to individual circuit boards, with each board having its own TBC. This segmentation maintains timing accuracy by limiting the length of TAP chains that need to be synchronized, while the distributed TBC architecture provides the necessary control and coordination across multiple boards without requiring complex multi-board TAP chain management.
Data Source
AI summary
Apparatus and other embodiments associated with a distributed Joint Test Access Group (JTAG) test bus controller (TBC) architecture are described. One example method includes providing first on-board scan programming (OSP) data to a first circuit board configured with a first TBC and located in a computer. The example method also includes providing second OSP data to a second circuit board configured with a second test bus controller and located in the same computer. The example method also includes controlling OSP to be performed at least partially in parallel on the first circuit board and the second circuit board.