Distributed PMIC Layout for Low-Inductance Envelope Tracking

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Solution Overview

Problem

Mobile communication devices face increased power consumption and thermal dissipation due to high output power of mmWave RF signals, leading to unwanted distortions in envelope tracking systems, especially at high modulation bandwidths.

Innovation Solution

A distributed power management circuit with a main PMIC and multiple distributed PMICs, reducing trace inductance by generating voltages closer to power amplifier circuits, thereby minimizing distortions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single centralized PMIC is used to generate voltages for power amplifier circuits, then device complexity is reduced, but trace inductance increases causing unwanted distortion in RF signals

Engineering Contradiction:
ImprovePMIC structure complexityVSAvoidRF signal distortion
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the centralized PMIC into multiple distributed PMICs, each serving specific power amplifier circuits. This segmentation reduces the trace inductance between voltage sources and power amplifier circuits, thereby reducing RF signal distortion while maintaining manageable device complexity through modular architecture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent places distributed PMICs locally near their respective power amplifier circuits to minimize trace inductance. Each distributed PMIC provides voltage locally, ensuring high-quality power delivery with minimal distortion for each specific power amplifier circuit

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If multiple distributed PMICs are used to reduce trace inductance, then RF signal linearity improves, but device complexity increases

Engineering Contradiction:
ImproveRF signal linearityVSAvoidPMIC structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The system segments the power management function across multiple distributed PMICs, each responsible for specific power amplifier circuits. This segmentation improves RF signal linearity by reducing trace inductance while the modular nature keeps complexity manageable

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control circuit monitors the operation status of distributed PMICs and dynamically adjusts their configuration. This feedback mechanism optimizes the balance between RF signal linearity and device complexity by activating only the necessary distributed PMICs for current operating conditions

Inventive Principle:
Principle #23Feedback

3Object-affected harmful factors

If distributed PMICs are placed closer to power amplifier circuits, then trace inductance is reduced, but the circuit layout complexity increases

Engineering Contradiction:
ImproveTrace inductance effectsVSAvoidCircuit layout complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent implements local voltage generation by placing distributed PMICs adjacent to their respective power amplifier circuits. This local quality approach minimizes trace inductance and its harmful effects while the standardized modular design keeps layout complexity manageable

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The distributed power management circuit reduces unwanted distortion in both main and distributed power amplifier circuits, enhancing linearity and overall performance by shortening conductive paths and reducing ripple effects.

Implementation Method 1

the time-variant ET voltage(s) can be highly susceptible to distortions caused by trace inductance

Methodology Applied
Scientific EffectTrace inductance: Inductor

Implementation Method 2

Each of the multiple voltage circuits is configured to generate a respective one of multiple voltages and/or a respective one of multiple low-frequency currents based on a respective one of multiple target voltages

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20240243708A1Distributed power management circuit
Publication Date: 2024.07.18 QORVO US INC
  • US20240243708A1 patent drawing
  • US20240243708A1 patent drawing
  • US20240243708A1 patent drawing

AI summary

A distributed power management circuit is provided. The distributed power management circuit includes a main power management integrated circuit (PMIC) and multiple distributed PMICs separated from the main PMIC. The main PMIC is configured to generate a number of voltages for a set of main power amplifier circuits located closer to the main PMIC and the distributed PMICs are configured to generate multiple distributed voltages for a set of distributed power amplifier circuits located closer to the distributed PMICs. In this regard, it is possible to reduce trace inductance between the main PMIC and the set of main power amplifier circuits and between the distributed PMICs and the distributed power amplifier circuits. As a result, it is possible to reduce unwanted distortion in both the main power amplifier circuits and the distributed power amplifier circuits.