Distributed Processor Architecture for Low-Way, High-Latency Memory
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Solution Overview
Problem
The von Neumann bottleneck in conventional computer architecture limits processing speeds due to throughput limitations in data transfer from memory to the processor, particularly in memory-intensive processes like neural networks and database operations, leading to inefficient use of clock cycles and computational bandwidth.
Innovation Solution
Distributed processor chips with dedicated memory banks and buses, eliminating arbiters and timing hardware logic, allowing processor subunits to operate in parallel with dedicated memory instances, and using buses to connect processor subunits and memory banks without external control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional computer architecture with shared memory and processor is used, then device complexity is reduced, but processing speed deteriorates due to von Neumann bottleneck
Solution Approach 1:
The system segments the monolithic processor and memory into multiple processor subunits and memory banks, each with dedicated interconnects. This segmentation eliminates the von Neumann bottleneck by allowing parallel data access and processing across multiple independent pathways, thereby improving processing speed while distributing system complexity across modular components.
Solution Approach 2:
The patent transitions from a single-bus, sequential architecture to a multi-dimensional mesh network where processor subunits can access memory banks through multiple routing paths. This dimensional expansion of the interconnect topology enables simultaneous data transfers and reduces contention, improving throughput without proportionally increasing complexity.
2Productivity
If dedicated memory banks and buses are used for each processor subunit, then processing efficiency improves, but device complexity increases
Solution Approach 1:
The mesh network interconnect provides universal connectivity where any processor subunit can access any memory bank through multiple possible paths. This multi-functional interconnect structure handles both local and remote accesses efficiently, improving processing efficiency while using a standardized, scalable topology that doesn't linearly increase complexity with system size.
Solution Approach 2:
The system performs preliminary routing decisions at the network level rather than requiring complex arbitration at each access point. Data packets include destination information that enables direct routing through the mesh network, eliminating the need for centralized arbiters and reducing timing hardware logic while maintaining high processing efficiency.
3Speed
If arbiters and timing hardware logic are included for data transfer control, then data transfer reliability improves, but processing speed deteriorates
Solution Approach 1:
The mesh network implements self-service routing where processor subunits and memory banks autonomously manage data transfer without external arbitration. Each node independently determines routing paths and manages data flow based on embedded address information, eliminating the need for speed-reducing arbiters while maintaining reliable transfers through decentralized control mechanisms.
Solution Approach 2:
The patent extracts the arbitration and timing control functions from the data path, removing them as separate hardware components that would slow down transfers. Instead, control information is embedded within data packets, and routing decisions are made locally at network nodes, separating control plane operations from data plane throughput and enabling high-speed transfers without sacrificing reliability.
4Productivity
If processor subunits operate in parallel with dedicated memory instances, then effective processing speed improves, but manufacturing complexity increases
Solution Approach 1:
Each processor subunit is designed with local quality - dedicated connections to specific memory banks and localized control logic. This modularity allows identical or similar subunits to be manufactured using the same processes and then configured for specific roles through routing tables, improving effective processing speed while simplifying manufacturing through repetition of standardized building blocks.
Solution Approach 2:
The system employs a nested hierarchical structure where processor subunits and memory banks are organized in levels, with each level containing multiple instances of the same modular component. This nesting allows the system to scale by repeating standardized units, improving processing throughput while maintaining manufacturing simplicity through hierarchical design that can be fabricated using standard semiconductor processes.
Data Source
AI summary
Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.