Associative Processors TRIZ Cases
- Redundant Vehicle Processing Architecture for ASIL-D Fail-Operational Control
Multiple simple and parallel processors with monitored redundancy keep vehicle automation running through faults while meeting ASIL-D safety needs.
- On-Chip Game and AI Engines for Local Real-Time ML Processing
Dedicated on-chip game and AI engines avoid server data transfer, improving real-time machine learning speed, privacy, and control.
- Distributed Processor Architecture for Low-Way, High-Latency Memory
Low-way, high-latency memory instances pair with local processor subunits and buses to improve parallel data access without centralized arbitration.
- Processor Local Bus Atomic Event Signaling for Multi-Core Communication
Atomic event signaling over a processor local bus enables concurrent multi-core communication without dedicated interrupt lanes.
- Scalable Alternation Network for Content Addressable Memory
A scalable alternation network splits matching vectors into odd and even components using cascaded logic gates to enable fast asynchronous data propagation.
- External AXU Interface for Off-Chip Instruction Format Conversion
An external auxiliary execution unit interface connects a processing core to an off-chip execution unit for instruction format conversion.
- Multi-Unit Processor Task Distribution for Power Efficiency
Segmenting a processor into dedicated processing units reduces CPU load and power consumption while maintaining system operation efficiency.
- Shift Buffer Chaining for AI Accelerator Data Reuse
Shift buffers chain input data to systolic arrays, minimizing repetitive memory access and energy consumption during convolution operations.