Processor Local Bus Atomic Event Signaling for Multi-Core Communication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for on-chip communication between multiple processors and data-handling engines in integrated circuits are inefficient, leading to delays and interference, as they rely on polling, dedicated interrupts, and serial mechanisms that restrict parallel processing and scalability.
Innovation Solution
A distributed signalling mechanism (DSM) using atomic data writes over a general-purpose communication bus, where data handlers prepare and send DSM signals with identification and data, allowing immediate notification and preventing race conditions, enabling efficient communication without dedicated interrupt lanes or memory locks, and allowing multiple data handlers to work concurrently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polling is used for communication between processors, then communication can be implemented, but processing power is wasted and delays are introduced
Solution Approach 1:
The patent replaces the mechanical polling system with an event-driven notification system. Instead of continuously checking for communication needs, processors use atomic operations to publish events and subscribe to specific event types. This substitution eliminates the time-consuming polling loop while maintaining reliable communication through event-driven architecture.
Solution Approach 2:
The communication system performs self-service by automatically notifying interested processors when events occur. The publishing processor simply sets the event in memory with atomic operations, and the notification mechanism automatically delivers it to subscribers without requiring continuous manual checking or polling from the publishing side.
2Reliability
If dedicated interrupt lines are used for processor communication, then signals can be sent reliably, but device complexity increases and scalability is restricted
Solution Approach 1:
The patent implements a universal communication bus that handles multiple types of signals (interrupts, data transfers, coordination messages) through a single shared infrastructure. Processors communicate by publishing atomic events on this universal bus, eliminating the need for dedicated interrupt lines for each processor pair while maintaining reliable signal delivery through atomic operation guarantees.
Solution Approach 2:
Instead of using physical dedicated wires for each communication channel, the system uses virtual channels implemented through software-defined event routing on a shared bus. The atomic operation mechanism creates virtual copies of signals that can be delivered to multiple destinations simultaneously without requiring physical duplication of wiring infrastructure.
3Productivity
If serial communication mechanisms are used between processors, then data can be transmitted, but only one message can be sent at a time introducing delay
Solution Approach 1:
The patent segments the communication stream into independent parallel channels using atomic operations with different addresses or identifiers. Multiple processors can simultaneously publish different atomic events on the same bus without conflict, and the system can route these events to different destinations in parallel, effectively creating multiple simultaneous communication channels rather than a single serial stream.
Solution Approach 2:
The system transitions from one-dimensional serial communication to multi-dimensional parallel communication by adding dimensions such as event types, destinations, and priorities. This allows multiple messages to be transmitted simultaneously across different dimensions of the event space, eliminating the bottleneck of sequential message processing.
4Reliability
If memory locks are used to protect data, then data integrity is maintained, but interference between data handlers occurs and accessibility is reduced
Solution Approach 1:
The patent extracts the locking mechanism from the data access process and replaces it with atomic operation primitives. Instead of using locks that block access, the system uses atomic compare-and-swap and atomic load/store operations that guarantee memory consistency without blocking. This extraction eliminates the interference caused by locks while maintaining data integrity through atomic guarantees.
Solution Approach 2:
The system replaces the mechanical lock-based synchronization with an atomic operation-based synchronization mechanism. Atomic operations provide memory consistency and data protection without the blocking behavior of locks, allowing multiple data handlers to access shared memory simultaneously without interference while maintaining integrity through atomic guarantees.
Data Source
AI summary
A heterogeneous multi-core integrated circuit comprising two or more processors, at least one of the processors being a general purpose CPU and at least one of the processors being a specialized hardware processing engine, the processors being connected by a processor local bus on the integrated circuit, wherein the general purpose CPU is configured to generate a first instruction for an atomic operation to be performed by a second processor, different from the general purpose CPU, the first instruction comprising an address of the second processor and a first command indicating a first action to be executed by the second processor, and transmit the first instruction to the second processor over the processor local bus. The first command may include the first action, or may be a descriptor of the first action or a pointer to where the first action may be found in a memory.