Divider Circuit Reducing Cycle Operations for High-Bit Processing
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Solution Overview
Problem
Current cycle dividers face increased complexity and operation costs as the bit numbers of the dividend and divisor increase, leading to a rise in the number of cycle operations required.
Innovation Solution
The proposed divider configuration includes at least one shift circuit, one selection circuit, and one operational circuit, which perform specific operations to reduce the number of cycle operations by shifting and selecting operands efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the bit numbers of the dividend and divisor increase, then the processing capability of the divider is improved, but the number of cycle operations increases and the apparatus complexity rises
Solution Approach 1:
The divider is divided into multiple stages, with each stage processing a specific number of bits. The first stage processes high-order bits and the second stage processes low-order bits, allowing parallel processing that reduces the total number of cycle operations while maintaining the ability to handle increased bit numbers
Solution Approach 2:
The invention introduces a multi-dimensional processing approach by organizing the division operation into multiple stages that process different bit segments simultaneously. This transforms the traditional single-dimensional sequential processing into a multi-dimensional parallel structure, reducing operation cycles while handling larger bit numbers
2Measurement precision
If the bit numbers of the dividend and divisor increase, then the processing capability of the divider is improved, but the number of cycle operations increases
Solution Approach 1:
The division operation is segmented into multiple stages, where each stage processes a specific portion of the bits. This segmentation enables parallel processing of different bit segments, significantly reducing the total number of cycle operations required while maintaining accurate division results for increased bit numbers
Solution Approach 2:
The first stage performs preliminary processing on the high-order bits of the dividend and divisor, generating intermediate results that are then used by the second stage. This preliminary action allows the system to handle increased bit numbers more efficiently by breaking down the overall operation into manageable segments that can be processed in parallel
Data Source
AI summary
This disclosure relates to a divider, a processor, and a calculation apparatus. The divider includes: a first-stage shift circuit, configured to shift a received first operand to left to generate a second operand; a first-stage selection circuit, configured to select a first preset multiple of a third operand as a fourth operand from preset multiples of the third operand; and a first-stage operational circuit, configured to calculate an OR operation result of the first preset multiple and a difference between the second operand and the fourth operand as a fifth operand.