Delay-Locked Loop Calibration for Stable Phase Alignment
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Solution Overview
Problem
Existing delay locked loop circuits face challenges in maintaining precise calibration and stability across variations in process, voltage, and temperature (PVT), leading to incorrect phase alignment due to limited control voltage ranges.
Innovation Solution
A delay locked loop circuit with a voltage-controlled delay line and a feedback circuit that operates in both calibration and active modes, using a fixed voltage source and a delay code setter to calibrate the delay code during calibration mode, and switches to feedback voltage in active mode, maintaining the control voltage within a stable range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the control voltage range is limited in existing delay locked loop circuits, then the circuit structure is simpler, but the phase alignment precision deteriorates under PVT variations
Solution Approach 1:
The patent applies preliminary calibration action by introducing a calibration mode that executes before normal operation. During calibration mode, the delay code is pre-adjusted to compensate for PVT variations, ensuring accurate phase alignment when the circuit enters active mode. This preliminary calibration resolves the contradiction by achieving high precision without requiring a complex continuously-adjusting control voltage range.
Solution Approach 2:
The patent introduces dynamic switching between calibration mode and active mode. The mode selection circuit dynamically transitions the circuit between these states based on operational requirements. During calibration mode, the delay line is adjusted to optimal settings; during active mode, the pre-calibrated settings are maintained. This dynamic approach achieves high precision phase alignment with a simple fixed control voltage range.
2Adaptability or versatility
If the control voltage varies widely to accommodate PVT changes, then the adaptability improves, but the stability of control voltage deteriorates
Solution Approach 1:
The calibration mode performs preliminary adjustment of the delay code to account for PVT variations. By pre-calibrating the delay line during manufacturing or initialization, the circuit adapts to different PVT conditions without requiring wide control voltage variations during normal operation. This maintains control voltage stability while achieving adaptability through the pre-set delay code.
Solution Approach 2:
The patent implements feedback mechanism where the calibrated delay code is fed back to the delay line configuration. The calibration process monitors phase alignment and adjusts the delay code accordingly, creating a feedback loop that optimizes performance. This feedback approach enables adaptability to PVT changes while maintaining stable control voltage during active operation.
3Measurement precision
If calibration is performed continuously to maintain precision, then the phase alignment accuracy improves, but the power consumption and operation time increase
Solution Approach 1:
The patent implements periodic calibration by switching between calibration mode and active mode. Calibration is performed periodically (e.g., during initialization or at scheduled intervals) rather than continuously. The mode selection circuit manages this periodic switching, allowing the circuit to maintain high phase alignment accuracy through regular calibration while minimizing the time spent in calibration mode during normal operation.
Solution Approach 2:
The dynamic mode switching between calibration and active states allows the circuit to optimize its operation. During active mode, the pre-calibrated settings are used for efficient operation with minimal time loss. When recalibration is needed, the circuit dynamically transitions to calibration mode, performs the necessary adjustments, and then returns to active mode. This dynamic approach balances accuracy maintenance with operational efficiency.
Data Source
AI summary
A delay locked loop (DLL) circuit includes a voltage-controlled delay line (VCDL) that applies a time delay to a clock-in signal to provide a first output signal and a last output signal. The magnitude of the time delay is based on the control-voltage signal and a delay code. The DLL circuit includes a feedback circuit configured to provide a feedback voltage signal based on the phase difference between the first output signal and the last output signal. In a calibration mode: a fixed voltage source provides a fixed voltage signal as the control-voltage signal for the VCDL; and a delay code setter applies a delay code setting signal to the VCDL to identify a selected-delay-code as the code. In an active mode: the feedback circuit provides the feedback voltage signal as the control-voltage signal for the VCDL; and the VCDL uses the selected-delay-code as the delay code.