DLL Clock Tracking with Delay Cell Reset for Accurate Locking
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Solution Overview
Problem
Delay locked loops (DLLs) often falsely lock onto improper delay times, leading to increased power consumption when the reference clock signal slows down, as they require more delay cells to maintain synchronization.
Innovation Solution
A method that involves allowing an external clock signal to pass through delay cells during specific periods, counting the number of delay cells, and resetting the delay time of each cell to maintain a ratio within a 10% to 15% range, ensuring accurate locking while controlling power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference clock signal slows down, then more delay cells are used to maintain synchronization, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the delay time of each delay cell adjustable rather than fixed. The control circuit dynamically changes the delay time based on the actual frequency of the reference clock signal, allowing the DLL to adapt to different operating conditions and optimize power consumption while maintaining synchronization accuracy.
Solution Approach 2:
The patent changes the delay time parameter of the delay cells based on the reference clock frequency. By monitoring the frequency and adjusting the delay time accordingly, the system maintains proper synchronization while avoiding the use of excessive delay cells that would increase power consumption.
2Reliability
If the delay time is increased to track slower clock signals, then synchronization is maintained, but the delay time to period ratio exceeds the optimal range
Solution Approach 1:
The patent employs feedback by continuously monitoring the frequency of the reference clock signal and using this information to adjust the delay time of the delay cells. This closed-loop control ensures that the delay time to period ratio remains within the optimal 10% to 15% range, maintaining locking accuracy while preventing excessive delay accumulation.
3Device complexity
If a fixed delay time is used in delay cells, then the structure is simple, but the DLL may falsely lock onto improper delay times
Solution Approach 1:
The patent transforms the static fixed delay time into a dynamic adjustable parameter. The control circuit modifies the delay time of each delay cell based on the reference clock frequency, enabling the system to avoid false locking while maintaining relatively simple delay cell structures that can be controlled through external signals.
Data Source
AI summary
A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay cells through which the external signal pass during the first period of the external clock signal is counted. When a reset signal is asserted, a delay time of each delay cell is reset such that a ratio of the delay time to the period of the external clock signal is kept from 10% to 15%.