DLL Clock Pulse Gating for Low-Power DRAM Idle Mode
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Solution Overview
Problem
Dynamic random access memory (DRAM) chips in computer systems face high power consumption due to the need to maintain delay-locked loops (DLLs) in idle mode to avoid latency, as turning off and re-locking DLLs is inefficient.
Innovation Solution
A clock gating circuit, referred to as the command and address clock (CAclk) pulse swallower, is used to apply a reduced activity clock to the DLL during idle mode, reducing power consumption by selectively masking transitions in the clock signal and maintaining the DLL's ability to track voltage and temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the DLL is kept on during idle mode to avoid latency, then the turn-on time is reduced, but power consumption increases
Solution Approach 1:
The patent applies periodic action by switching the DLL between active and idle modes based on whether data is being transferred. When the memory device is not performing data transfers, the DLL is placed in idle mode to save power. When data transfers are needed, the DLL is activated. This periodic switching resolves the contradiction by allowing the system to consume less power during idle periods while maintaining quick response capability when needed.
Solution Approach 2:
The patent implements preliminary action by maintaining the DLL in a partially prepared state during idle mode rather than completely shutting it down. The DLL retains its basic structure and configuration but operates at reduced activity, allowing it to quickly resume full operation when data transfers are needed. This preliminary preparation resolves the contradiction by enabling fast turn-on without requiring the DLL to be fully active continuously.
2Use of energy by moving object
If the DLL is turned off to save power, then power consumption is reduced, but re-locking time increases significantly
Solution Approach 1:
The patent applies dynamics by making the DLL operational state flexible and adaptable. Instead of a static on/off state, the DLL transitions between active, idle, and locked states based on system needs. The DLL can be dynamically adjusted to operate at different activity levels, allowing power savings during idle periods while maintaining the capability to quickly re-lock when data transfers are required. This dynamic approach resolves the contradiction between power consumption and re-locking time.
3Use of energy by moving object
If the DLL operates at reduced activity clock during idle mode, then power consumption is reduced, but the ability to track voltage and temperature changes may be affected
Solution Approach 1:
The patent applies parameter changes by adjusting the clock activity level of the DLL based on operational mode. During idle mode, the DLL operates at a reduced activity clock frequency to minimize power consumption. When data transfers are needed, the DLL switches to full activity mode to properly track voltage and temperature changes. This parameter adjustment resolves the contradiction by allowing reduced power consumption during idle periods while maintaining full tracking capability when reliability is critical.
Data Source
AI summary
Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.