DLL Control Circuit for Faster DRAM Clock Locking
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Solution Overview
Problem
The prolongation of locking time in DRAM due to extended clock cycles caused by the DLL circuit's delay operation exceeds the predetermined program execution period, leading to inefficiencies in semiconductor memory devices.
Innovation Solution
A control circuit with a detection unit that performs multiple N value detection operations before the delay operation, allowing the control unit to set an optimal delay amount based on false N values, thereby synchronizing the input and output clock signals within a predetermined execution period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit performs delay operation with extended clock cycles, then the internal clock signal can be synchronized with input clock signal, but the locking time is extended and exceeds the program execution period
Solution Approach 1:
The detection unit performs multiple detection operations to determine the number of delayed clock cycles before the delay operation is executed. This preliminary detection allows the control unit to set an appropriate delay amount in advance, preventing extension of the locking time and ensuring completion within the program execution period while maintaining reliable clock signal synchronization.
2Reliability
If the delay amount is increased to synchronize clock signals, then the locking time is extended, but the program execution period is exceeded
Solution Approach 1:
The detection unit performs multiple detection operations to obtain feedback information about the number of delayed clock cycles. The control unit uses this feedback to dynamically set the delay amount, ensuring that the delay operation completes within the program execution period while achieving reliable clock signal synchronization.
Solution Approach 2:
The delay amount is dynamically adjusted based on the detection results from multiple detection operations. This dynamic adjustment allows the system to optimize the delay amount for each specific condition, preventing excessive locking time and ensuring program execution completes within the required period.
Data Source
AI summary
A control circuit includes a control unit, a delay line unit, and a detection unit. The delay line unit delays an input clock signal based on the delay amount and generates an output clock signal. The detection unit performs a detection operation to detect the number of delayed clock cycles from the input clock signal to the output clock signal. The control unit changes the delay amount during a delay operation and controls the delay line unit so that the input clock signal is synchronized with the output clock signal. Before the delay operation, the detection unit performs the detection operation multiple times and detects a plurality of numbers of delayed clock cycles. The control unit sets the delay amount for the detection operation and sets the delay amount for the delay operation according to plurality of detected numbers of delayed clock cycles.