DLL Clock Control Circuit for Shorter DRAM Locking Time
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Solution Overview
Problem
Existing DRAM technologies face challenges in maintaining efficient synchronization of internal and external clock signals due to prolonged locking times caused by temperature variations, leading to delayed sequence execution and complex structural modifications for speed enhancement.
Innovation Solution
A control circuit with a delay control unit and clock control unit that adjusts the input clock signal based on phase differences, using a clock control unit to select either a first or second clock signal to minimize phase differences and reduce locking times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit performs delay operation to synchronize internal clock with external clock, then phase synchronization is achieved, but locking time is prolonged when temperature causes clock period to be longer than existing delay time
Solution Approach 1:
The patent applies preliminary action by performing a preliminary delay adjustment before the main delay operation. The control circuit first determines whether the phase difference exceeds a predetermined threshold, and if so, performs an initial delay adjustment to bring the phase difference within the threshold range. This preliminary action prevents the need for excessively long delay operations, thereby reducing locking time while ensuring phase synchronization is achieved.
2Reliability
If the delay operation is extended to handle temperature variations, then synchronization reliability is improved, but sequence execution time increases and may exceed the execution period
Solution Approach 1:
The control circuit performs a preliminary check of the phase difference before initiating the full delay operation. When the phase difference is within the predetermined threshold, the circuit skips unnecessary delay steps, allowing the sequence to complete within the execution period while still achieving reliable synchronization.
3Productivity
If the structure is modified to increase speed of delay operation, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent achieves faster delay operation without increasing structural complexity by using a preliminary phase difference check. The control circuit determines whether preliminary delay adjustment is needed based on the phase difference threshold, enabling speed optimization through intelligent control logic rather than complex hardware modifications.
Data Source
AI summary
A control circuit is provided herein, which can suppress the prolongation of a delay operation, so that the sequence using the DLL circuit to adjust the delay of the internal clock signal can be finished within a predetermined execution period. A control circuit includes a delay control unit delaying an input clock signal to generate an output clock signal based on the phase difference between the input clock signal and an output clock signal. The control circuit further includes a clock control unit. When the phase difference is greater than the first predetermined amount, the clock control unit inputs a clock signal delayed from the input clock signal by a second predetermined amount to the delay control unit as the input clock signal.