Delay-Locked Loop Clock Modeling for Internal Path Phase Correction
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Solution Overview
Problem
Semiconductor apparatuses face a challenge in maintaining synchronization between input and internal clock signals due to differences between modeled and actual delay values in the internal clock path, which can reduce the timing margin of internal circuits.
Innovation Solution
A semiconductor apparatus is designed with a DLL that includes a delay model unit and a detection code/output block to generate phase difference detection codes or a control voltage based on the phase difference between modeled and actual delay values, allowing for phase correction and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a delay model unit is used to model the delay value of the internal clock path, then the phase control of the DLL clock signal can be implemented, but a difference between the model delay value and the actual delay value occurs, reducing timing margin
Solution Approach 1:
The patent introduces a feedback mechanism where the output of the internal clock path is fed back to a phase comparator. The phase comparator compares the phase of the feedback signal with the phase of the DLL clock signal, generating a phase difference signal. This phase difference signal is used to adjust the delay model unit, creating a closed-loop system that continuously corrects the phase difference between the modeled and actual delay values, thereby maintaining timing margin while preserving phase control capability.
Solution Approach 2:
The patent creates a more accurate copy of the internal clock path delay by using the actual output signal from the internal clock path itself as the reference for phase comparison. Instead of relying solely on a pre-modeled delay value, the system uses the actual delayed signal to generate the phase difference detection signal, which then adjusts the delay model to better match the actual delay characteristics, reducing the discrepancy between model and reality.
2Ease of manufacture
If the positions of components in the delay model unit are made different from actual components to simplify modeling, then the modeling process becomes easier, but the delay value accuracy decreases
Solution Approach 1:
The feedback mechanism continuously measures the actual delay characteristics through phase comparison and automatically adjusts the delay model unit to match the actual internal clock path delay. This closed-loop adjustment compensates for any simplifications or inaccuracies in the initial modeling, maintaining high delay value accuracy without requiring the model to perfectly replicate the physical component positions.
Solution Approach 2:
The system dynamically changes the delay parameters of the delay model unit based on the phase difference detection signal. By adjusting the delay values in the model unit according to the measured phase difference, the system optimizes the accuracy of the delay model without being constrained by fixed component positions, allowing flexible parameter tuning to achieve precise delay matching.
Data Source
AI summary
A delay locked loop semiconductor apparatus that models a delay of an internal clock path is presented. The semiconductor apparatus includes: a DLL and a detection code output block. The DLL includes a delay model unit in which a delay value of an internal clock path is modeled and is configured to output a DLL clock signal of which the phase is controlled by reflecting the delay value of the internal clock path into an applied input clock signal. The detection code output block is configured to output a phase difference detection code having a code value corresponding to a phase difference between a first phase correction clock signal generated by reflecting a model delay value of the delay model unit into the DLL clock signal and a second phase correction clock signal generated by reflecting an actual delay value of the internal clock path into the DLL clock signal.