Frequency-Multiplying DLL for Low-Jitter Clock Phase Generation
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Solution Overview
Problem
Existing frequency multiplication techniques in electronic systems, such as phase-locked loops (PLLs) and clock edge cycling methods, are complex, costly, and suffer from high jitter and phase spacing errors, making them unsuitable for high-speed interconnects with forwarded clock architectures.
Innovation Solution
The implementation of a frequency multiplying delay-locked loop (DLL) circuit that increases the frequency of an incoming clock signal while generating multiple phase-shifted output signals using a multiplier portion and an array of delay cells, ensuring even spacing of clock phases through shared voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a phase-locked loop (PLL) is used for frequency multiplication, then frequency multiplication is achieved, but the device complexity and silicon area increase
Solution Approach 1:
The frequency multiplying DLL is divided into distinct functional segments: a delay element array with N elements that generates phase-shifted signals, a phase detector that compares input clock phases, a charge pump that converts phase differences to current, and a loop filter that regulates the control voltage. This segmentation allows each component to be optimized independently while reducing overall complexity compared to traditional PLL architectures.
2Productivity
If a phase-locked loop (PLL) is used for frequency multiplication, then frequency multiplication is achieved, but the jitter increases
Solution Approach 1:
The system employs a feedback mechanism where the phase detector continuously monitors the phase relationship between the input clock and the feedback clock derived from the delay element array. The charge pump generates correction currents based on phase detection results, and the loop filter smooths these corrections to adjust the VCO frequency, thereby reducing jitter through continuous feedback control.
Solution Approach 2:
The delay element array pre-generates multiple phase-shifted versions of the input clock signal before frequency multiplication. By having these phase-shifted signals ready in advance, the system can select the appropriate phase without requiring complex real-time adjustments, thereby reducing jitter in the final output.
3Productivity
If clock edges are cycled through a multiplexer with a state machine, then frequency multiplication is achieved, but phase spacing errors occur
Solution Approach 1:
The phase detector acts as an intermediary that precisely measures the phase difference between input clock signals and feedback signals. This intermediary component provides accurate phase information to the charge pump, enabling precise control of the VCO frequency and ensuring even phase spacing in the multiplied output signals without the errors introduced by multiplexer-based approaches.
4Productivity
If separate multipliers are used for each phase after phase generation, then frequency multiplication is achieved, but the device complexity and cost increase
Solution Approach 1:
The delay element array serves multiple functions simultaneously: it generates phase-shifted signals for frequency multiplication, provides feedback signals for phase detection, and enables jitter reduction through its inherent delay characteristics. This multi-functionality eliminates the need for separate multiplier circuits for each phase, reducing overall device complexity while maintaining frequency multiplication capability.
Data Source
AI summary
Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated utilizing a delay-locked loop circuit having a clock multiplication, the phase shifted signals having increased frequency relative to the incoming signal. The phase-shifted signals being generated by the delay-locked loop in order to position the clock to an optimal detection point of incoming data signals.