Delay-Locked Loop Clock Selection for Long-Period Synchronization
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Solution Overview
Problem
The existing delay locked loops in semiconductor memory devices face challenges in achieving proper delay locking operations when the inputted clock has a long cycle period, as the maximum delay value of the delay unit is not sufficient, leading to issues with synchronization and data output timing.
Innovation Solution
A semiconductor device with a delay unit, selection unit, and selection control unit that allows for adjustable delay operations by comparing the inputted clock and feedback clock phases, enabling selection between the inputted clock and delayed clock to ensure synchronization, even when the maximum delay value is exceeded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the delay unit is designed with a fixed maximum delay value, then the circuit structure remains simple, but the delay locked loop cannot perform proper delay locking operations when the inputted clock has a long cycle period
Solution Approach 1:
The delay unit is divided into multiple sub-delay units (first delay unit, second delay unit, third delay unit) that can be selectively activated. Each sub-delay unit provides a specific delay value, allowing the system to segment the total delay requirement into manageable portions that can be combined to match the input clock period.
Solution Approach 2:
The delay unit transitions from a static fixed delay configuration to a dynamic configurable delay structure. The selection control unit dynamically selects which sub-delay units to activate based on the input clock period, enabling the delay locked loop to adapt to varying clock frequencies while maintaining a relatively simple overall circuit architecture.
2Reliability
If the maximum delay value of the delay unit is increased to handle long cycle periods, then delay locking operation is improved, but the operating frequency range becomes limited and bang-bang jitter increases
Solution Approach 1:
Instead of using a single large delay unit with maximum delay value, the system segments the delay into multiple smaller sub-delay units. This allows the system to achieve the required total delay for long cycle periods by activating multiple sub-units in series, while still maintaining the ability to operate at higher frequencies by activating fewer or no sub-units.
Solution Approach 2:
The system changes the delay parameter dynamically by selecting different combinations of sub-delay units based on the input clock period. This allows the delay locked loop to maintain reliable operation across a wide frequency range by adjusting the effective delay value to match the specific operating conditions.
3Ease of manufacture
If the delay unit uses a fixed delay configuration, then the circuit is simple to manufacture, but synchronization accuracy deteriorates when the input clock period varies
Solution Approach 1:
The delay unit is segmented into multiple standardized sub-delay units with predetermined delay values. This segmentation allows the system to maintain manufacturing simplicity by using repeated, standardized circuit blocks while achieving variable delay configurations through selective activation of these blocks.
Solution Approach 2:
The sub-delay units are designed as universal, multi-functional blocks that can be activated in different combinations to provide various delay values. This universal design simplifies manufacturing by using the same basic circuit block multiple times, while the selection control unit provides the flexibility to achieve accurate synchronization for different clock periods.
Data Source
AI summary
A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the delay clock, a delay locked loop configured to perform a delay locking operation using a signal delivered from the selection unit, and a selection control unit configured to control the selection unit in response to a comparison of one period of the inputted clock and a maximum delay value of the delay locked loop.