DLL Clock Skew Compensation in Semiconductor Memory Output Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining data input/output speed synchronization with increasing processor speeds due to clock signal delays, leading to data skew errors during high-speed operations.
Innovation Solution
A semiconductor memory device with a DLL circuit that generates DLL clocks with different phases and includes a skew compensating unit to remove clock skew between these clocks, ensuring data is outputted in synchronization with the system clock, using a phase comparator, delay chain, delay controller, clock skew compensator, and replica model to adjust delay values and compensate for clock skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the data output circuit outputs data in synchronization with the delayed system clock, then the data output timing is simplified, but the data becomes desynchronized with the system clock edges at external devices
Solution Approach 1:
The patent introduces a DLL circuit as an intermediary component between the system clock and data output circuit. The DLL circuit receives the system clock, compensates for internal delays, and generates a corrected clock signal that synchronizes data output with external device expectations, thus resolving the contradiction between simplified output timing and synchronization accuracy
Solution Approach 2:
The DLL circuit employs feedback mechanisms to detect and compensate for clock signal delays. By continuously monitoring the phase relationship between the system clock and the delayed clock, the DLL adjusts delay elements to maintain proper synchronization, ensuring data is output at the correct timing relative to system clock edges
2Productivity
If the operating speed of the semiconductor memory device is increased to match the data processor speed, then the data I/O speed improves, but clock signal delays cause data skew errors
Solution Approach 1:
The patent implements dynamic delay adjustment mechanisms within the DLL circuit that can adapt to varying operating conditions and speeds. The delay elements are made controllable and adjustable, allowing the system to optimize timing compensation at different data I/O speeds, thus maintaining reliability while improving productivity
Solution Approach 2:
The DLL circuit changes the delay parameter of clock signals dynamically based on operating conditions. By adjusting delay values in response to different data I/O speeds and timing requirements, the system maintains accurate synchronization across a range of operating speeds, resolving the contradiction between speed and timing accuracy
3Productivity
If DLL clocks with different phases are generated to maximize timing for multiple data operations, then data processing capability improves, but delay skew occurs between DLL clocks
Solution Approach 1:
The patent applies different delay compensation values to different DLL clock phases individually. Each phase receives customized delay adjustment tailored to its specific timing requirements and path delays, ensuring that while phases differ in timing, each is precisely compensated for its particular characteristics, thus maintaining overall timing precision
Data Source
AI summary
A semiconductor memory device includes a delay locked loop (DLL) unit configured to generate a plurality of DLL clocks, each having a different phase according to delay values predefined by a DLL operation; a data output buffering unit configured to output data in response to the DLL clocks; and a skew compensating unit disposed between the DLL unit and the data output buffering unit to remove a clock skew occurring when the DLL clocks are transferred to the data output buffering unit.