DLL Delay Chain Rerouting for Reduced Duty Cycle Distortion
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Solution Overview
Problem
Existing delay-locked loop (DLL) circuits face challenges in achieving a reliable phase shift over a wide frequency range, particularly for high-frequency data capture in DDR memory applications, due to limitations in phase options and duty cycle distortion, which are exacerbated by constraints across process, supply voltage, and temperature (PVT) corners.
Innovation Solution
A DLL circuit design incorporating 8 delay circuit elements with a phase detector and up/down counter, using variable and fixed delay blocks to dynamically adjust delays and reroute signals, ensuring even phase offsets and minimizing duty cycle distortion through Gray-coded control signals and decoding schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay circuits are used in DLL, then the circuit can operate at basic frequencies, but duty cycle distortion accumulates and phase accuracy deteriorates across PVT variations
Solution Approach 1:
The delay circuit is segmented into multiple delay elements (first delay element, second delay element, third delay element) with distinct functions. The first delay element provides baseline delay, the second delay element provides adjustable delay controlled by Gray-coded signals, and the third delay element compensates for duty cycle distortion. This segmentation allows each segment to address specific aspects of the problem, preventing distortion accumulation while maintaining phase accuracy across PVT variations.
Solution Approach 2:
The DLL circuit incorporates a feedback mechanism where the phase detector compares the input clock signal with the delayed output signal and generates control signals to adjust the delay elements. This feedback loop continuously corrects phase errors and compensates for duty cycle distortion, ensuring reliable phase accuracy despite PVT variations. The feedback control signals dynamically adjust the delay elements to maintain optimal performance.
2Adaptability or versatility
If more delay stages are added to support wide frequency range, then frequency coverage improves, but circuit complexity and distortion accumulation increase
Solution Approach 1:
The delay circuit employs dynamic delay adjustment through Gray-coded control signals that enable the delay elements to adapt their delay values in real-time. This dynamic capability allows the circuit to cover a wide frequency range by adjusting total delay without requiring additional static delay stages. The dynamic adjustment mechanism provides frequency adaptability while keeping the number of physical delay stages manageable, reducing complexity compared to static multi-stage designs.
Solution Approach 2:
The circuit changes delay parameters dynamically using Gray-coded control signals to adjust the delay of individual delay elements. By varying the delay parameters of existing elements rather than adding more stages, the circuit achieves wide frequency coverage. The parameter changes are controlled systematically through the Gray-coded signaling mechanism, allowing precise delay adjustment across the frequency range without proportionally increasing circuit complexity.
3Reliability
If standard delay circuits are used, then manufacturing is straightforward, but phase options are limited and cannot achieve reliable phase shift across PVT corners
Solution Approach 1:
The delay circuit elements are designed to perform multiple functions: the first delay element provides baseline delay, the second delay element provides adjustable delay for phase tuning, and the third delay element provides distortion compensation. This multi-functionality allows a single circuit implementation to achieve reliable phase shift across PVT corners while maintaining manufacturing feasibility. The universal design approach consolidates multiple required functions into integrated delay elements rather than requiring separate specialized circuits for each function.
Data Source
AI summary
A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.