Delay-Locked Loop Delay Measurement Using Multi-Cycle Pulse Timing
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Solution Overview
Problem
As memory working frequencies increase, accurately measuring path delays in delay-locked loops becomes challenging due to insufficient measurement margins, leading to potential loop delay measurement errors.
Innovation Solution
A delay measurement circuit is introduced, comprising a loop flag generation circuit and a counter circuit, which cycles a loop flag signal M times to measure loop delay, where M is an even number greater than 1, and uses a divided clock signal to time the valid pulse width, ensuring accurate loop delay measurement with a larger margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory working frequency is increased to improve productivity, then the data transmission speed is improved, but the measurement margin for path delay becomes insufficient leading to measurement errors
Solution Approach 1:
The loop delay measurement is segmented into multiple cycles (M times) to increase the measurement margin. By measuring the cumulative delay over M cycles and then dividing by M, the circuit achieves sufficient measurement precision even at high working frequencies where a single-cycle measurement would be insufficient.
Solution Approach 2:
The loop flag signal is cycled M times in advance before the actual measurement is completed. This preliminary cycling accumulates the loop delay M times, creating a larger measurement margin that can be accurately timed by the counter circuit using the divided clock signal.
2Loss of time
If a single cycle loop delay measurement is used to simplify the measurement process, then the measurement time is reduced, but the measurement margin is insufficient at high clock frequencies
Solution Approach 1:
The loop flag signal is cycled M times in advance before the actual measurement is completed. This preliminary cycling accumulates the loop delay M times, creating a larger measurement margin that can be accurately timed by the counter circuit using the divided clock signal.
Solution Approach 2:
The loop delay is copied and accumulated M times through repeated cycling of the loop flag signal. This creates a magnified version of the original delay that is easier to measure accurately, and the final result is obtained by dividing the total measured time by M.
3Measurement precision
If the loop delay measurement margin is increased to prevent measurement errors, then the measurement accuracy is improved, but the measurement time increases
Solution Approach 1:
The measurement approach changes from timing a single loop cycle to timing M loop cycles, where M is an even number greater than 1. This parameter change increases the measurement margin by a factor of M, improving accuracy. The use of a divided clock signal (with higher frequency) compensates for the increased measurement time, maintaining overall system efficiency.
Data Source
AI summary
A delay measurement circuit includes: a loop flag generation circuit configured to: generate a loop flag signal and input the loop flag signal to the loop of the delay-locked loop when loop delay measurement is performed on the delay-locked loop; and generate a measurement finish signal and generate a target pulse signal after the loop flag signal is cycled for M times in the loop of the delay-locked loop, a valid pulse width of the target pulse signal being equal to M times a loop delay; and a counter circuit configured to: receive a divided clock signal; time the valid pulse width of the target pulse signal based on the divided clock signal, to obtain a timing result; and perform preset processing on the timing result, to obtain a loop delay measurement result of the delay-locked loop.