DLL Delay Control Circuit for Overflow-Aware N-Value Detection
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Solution Overview
Problem
Conventional DRAMs face challenges in completing the N-value detection sequence within a predetermined period due to extended lock times caused by overflow states in the delay line, which can lead to malfunctions.
Innovation Solution
A delay control circuit comprising a DLL control circuit, a delay line circuit, and an N-value detection circuit that determines the delay amount based on phase differences and detects overflow states to prevent N-value detection operations when in overflow, thereby setting the N-value to a predetermined value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay line operates in overflow state (delay amount exceeds predetermined delay), then the lock time of the DLL circuit is extended, but the N-value detection sequence cannot be completed within the predetermined period
Solution Approach 1:
The invention performs preliminary detection of the overflow state before executing the N-value detection sequence. The DLL control circuit determines whether it is in an overflow state by checking whether the delay amount exceeds a predetermined delay amount. When overflow is detected, the system proactively skips the N-value detection operation and sets the N-value to a predetermined value, preventing the time extension problem before it occurs.
Solution Approach 2:
Instead of performing the N-value detection operation and then handling potential overflow issues, the invention inverts the approach by first detecting the overflow state and conditionally skipping the N-value detection operation. This reverse logic ensures that when overflow occurs, the system avoids the time-consuming detection sequence entirely, completing the operation within the predetermined period.
2Reliability
If the clock cycle is longer than the existing delay time (overflow state), then the lock time of the DLL circuit is extended, but the clock delay adjustment procedure exceeds the predetermined period
Solution Approach 1:
The system performs preliminary detection of the overflow state before initiating the clock delay adjustment procedure. By checking whether the delay amount exceeds the predetermined delay amount in advance, the system can determine the appropriate N-value without executing the full detection sequence, thereby maintaining fast adjustment speed while ensuring synchronization accuracy.
Solution Approach 2:
The DLL control circuit autonomously determines whether it is in an overflow state and automatically adjusts the N-value accordingly. When overflow is detected, the circuit self-corrects by setting the N-value to a predetermined value without requiring external intervention or lengthy detection procedures, thus maintaining both accuracy and speed.
3Measurement precision
If the N-value detection operation is performed in overflow state, then the lock time is extended, but the overall execution time exceeds the predetermined period tDLLK
Solution Approach 1:
The invention performs preliminary detection of the overflow state before executing the N-value detection sequence. When the DLL control circuit determines that it is in an overflow state, it proactively skips the N-value detection operation and sets the N-value to a predetermined value, ensuring that the detection sequence completes within the predetermined period while maintaining necessary accuracy through conditional logic.
Solution Approach 2:
Instead of always performing the complete N-value detection operation, the system applies partial action by skipping the detection step when overflow is detected. This conditional approach performs only the necessary minimum action (setting N-value to predetermined value) in overflow cases, reducing execution time while maintaining sufficient accuracy for the system's operation.
Data Source
AI summary
A delay control circuit provided herein includes a DLL control circuit, a delay line circuit, and an N-value detection circuit. The DLL control circuit determines the delay amount based on the phase difference between the input and output clock signals. The delay line circuit delays the input clock signal based on the delay amount to generate an output clock signal. The N-value detection circuit performs an N-value detection operation for detecting the number of delayed clock cycles from the input clock signal to the output clock signal. When it is determined to be in an overflow state, the DLL control circuit outputs a signal indicating an overflow state to the N-value detection circuit. When the signal indicating the overflow state is received, the N-value detection circuit does not perform the N-value detection operation, but instead sets the number of delayed clock cycles to a predetermined value.