Delay-Locked Loop Delay Measurement With Multi-Cycle Pulse Timing
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Solution Overview
Problem
As memory working frequencies increase, accurately measuring path delays in delay-locked loops becomes challenging due to insufficient measurement margins, leading to potential loop delay measurement errors and reduced accuracy.
Innovation Solution
A delay measurement circuit is introduced for delay-locked loops, utilizing a loop flag generation circuit to generate a loop flag signal and a target pulse signal after cycling for M times, where M is an even number greater than 1, and a counter circuit to time the valid pulse width based on a divided clock signal, ensuring accurate loop delay measurement with increased margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory working frequency is increased, then the productivity is improved, but the measurement precision of path delay deteriorates due to insufficient measurement margin
Solution Approach 1:
The patent segments the delay measurement process by introducing an initial delay period before the loop flag signal is generated. This initial delay segment allows the loop flag signal to stabilize and ensures sufficient measurement margin even at high working frequencies, thereby resolving the contradiction between high productivity and measurement precision
Solution Approach 2:
The patent performs preliminary action by pre-delaying the loop flag signal generation until after an initial period following the read command. This preliminary delay ensures that the measurement starts only after the system has stabilized, providing sufficient measurement margin for accurate path delay measurement at high frequencies
Data Source
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Figure 3A~3B
AI summary
Embodiments of the present disclosure provide a delay measurement circuit and a memory. The delay measurement circuit includes: a loop flag generation circuit, electrically connected to a loop of a delay-locked loop, and configured to: generate a loop flag signal and input the loop flag signal to the loop of the delay-locked loop when loop delay measurement is performed on the delay-locked loop; and generate a measurement finish signal and generate a target pulse signal after the loop flag signal is cycled for M times in the loop of the delay-locked loop, a valid pulse width of the target pulse signal being equal to M times a loop delay; and a counter circuit, electrically connected to the loop flag generation circuit, and configured to: receive a divided clock signal; time the valid pulse width of the target pulse signal based on the divided clock signal, to obtain a timing result; and perform preset processing on the timing result, to obtain a loop delay measurement result of the delay-locked loop. The embodiments of the present disclosure at least help to increase a margin of the delay measurement circuit and improve accuracy of loop delay measurement.