DLL Delay Reset Control for Stable Clock Locking Under PVT Variation
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Solution Overview
Problem
Conventional semiconductor devices with delay locked loops (DLLs) face challenges in precisely tracking the delay amount required for locking, especially under variations in process/voltage/temperature (PVT) conditions, leading to insufficient delay adjustments and potential failure in maintaining synchronization with external clock signals.
Innovation Solution
The semiconductor device incorporates a DLL configured to set a delay amount threshold and a DLL controller that activates a reset signal when the second delay amount deviates from a given range, allowing for adjustment of the first delay amount to a third delay amount, ensuring the delay amount for locking is sufficient even under PVT variations, by using a fourth delay amount when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the initial delay amount is set to a small value to reduce setup time, then the locking speed is improved, but the delay tracking precision deteriorates under PVT variations
Solution Approach 1:
The patent applies preliminary action by setting a large initial delay amount before the locking process begins. This ensures that even under PVT variations, the delay amount remains sufficient throughout the locking process. The large initial delay acts as a buffer that prevents the delay from becoming too small during tracking, thereby maintaining precision while still achieving acceptable locking speed.
2Reliability
If the initial delay amount is set to a large value to ensure sufficient delay under PVT variations, then the reliability is improved, but the locking time increases
Solution Approach 1:
The patent applies dynamics by making the delay amount adjustable and controllable throughout the locking process. The delay control unit dynamically adjusts the delay amount based on the locking state and PVT conditions. This allows the system to start with a large delay for reliability, then reduce it during locking to minimize locking time, achieving both reliability and speed requirements.
3Stability of the object's composition
If the delay control range is limited to prevent excessive delay adjustments, then the stability is improved, but the adaptability to PVT variations deteriorates
Solution Approach 1:
The patent applies another dimension by introducing a control dimension for the delay amount that is separate from the tracking direction. The delay control unit can adjust the delay amount in a controlled manner while the tracking unit continues to track phase differences. This adds a new degree of freedom that allows the system to maintain stability through controlled adjustments while still adapting to PVT variations when necessary.
Data Source
AI summary
A semiconductor device includes a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a reference clock signal in response to a second delay amount tracked using a first delay amount as an initial delay amount, and track the second delay amount again by adjusting the first delay amount in response to a reset signal, and a DLL controller configured to activate the reset signal when the second delay amount deviates from a given range.