DLL Duty Cycle Correction with Independent Edge Control
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits fail to correct the duty cycle, limiting the maximum frequency and speed of operation in high-speed circuits that use double data rate, where both rising and falling edges trigger data operations.
Innovation Solution
A DLL circuit with a duty cycle correction (DCC) loop that controls the falling edge to achieve a 50% duty cycle, using a shared delay line with independent controls for both edges, reducing circuit size and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DLL circuits are used to generate clock signals, then the circuit structure is simple, but the duty cycle cannot be corrected which limits the maximum frequency and speed of operation
Solution Approach 1:
The patent merges the DLL and DCC functions into a single integrated circuit structure. The shared delay line is used by both the DLL loop (for phase locking) and the DCC loop (for duty cycle correction), combining two previously separate functions into one unified device. This merging allows the circuit to achieve both phase-locked operation and 50% duty cycle correction without proportionally increasing circuit complexity
Solution Approach 2:
The delay line is designed to serve multiple functions: it provides phase delay for the DLL operation and simultaneously provides duty cycle correction when controlled by the DCC loop. The same physical delay line structure is universally used for both phase synchronization and duty cycle adjustment, making the circuit multi-functional and efficient
2Reliability
If separate delay lines are used for DLL and DCC functions, then each function can be optimized independently, but the overall circuit size and complexity increase
Solution Approach 1:
The patent combines the DLL delay line and DCC delay line into a single shared delay line structure. Both the DLL loop (controlling rising edges) and DCC loop (controlling falling edges) utilize the same delay line, eliminating the need for separate delay lines while maintaining independent control capability through separate control voltages (Vrise and Vfall)
Solution Approach 2:
The shared delay line is designed to be universally controllable for both DLL phase locking and DCC duty cycle correction. The delay line responds to control voltages from either the DLL charge pump or the DCC charge pump, making it a multi-functional component that replaces what would traditionally require two separate delay line structures
Data Source
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AI summary
A delay locked loop (DLL) circuit includes a delay line which receives an input clock, and provides an output clock which is phase shifted 360 degrees and an intermediate clock which is phase shifted less than 360 degrees from the input clock. A DLL loop receives the input clock as a DLL reference clock and the output clock as a DLL feedback clock, and outputs a first control voltage to adjust first edges of the input clock. A duty cycle correction (DCC) loop receives the intermediate clock as a DCC reference clock and an inverse of the output clock as a DCC feedback clock, and outputs a second control voltage to adjust second edges of the input clock, independent of the first edges of the input clock. The DCC loop is enabled after the DLL loop achieves lock between the first edges of the output clock and the input clock.