DLL Clock Jitter Feedback Circuit for Stable Phase Synchronization
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Solution Overview
Problem
Conventional clock circuits suffer from significant jitter due to component performance characteristics and varying operating conditions, leading to unpredictable and wide-ranging timing errors in clock signals.
Innovation Solution
A clock jitter feedback circuit with a dual delay locked-loop arrangement and a multi-signal phase detector is introduced to synchronize feedback signals, reducing jitter by adjusting delays and maintaining synchronization across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional DLL with model delay is used to synchronize clock signals, then clock signal synchronization is achieved, but significant jitter occurs due to component performance variations and operating condition changes
Solution Approach 1:
The patent implements a feedback mechanism by tapping the output clock signal and feeding it back through a model delay circuit to the phase detector. This closed-loop feedback allows the system to continuously monitor and correct phase deviations caused by jitter, thereby maintaining synchronization precision while compensating for component variations and operating condition changes
Solution Approach 2:
The patent applies preliminary action by using the model delay circuit to pre-compensate for expected propagation delays in the feedback path. The model delay is designed to match the delay characteristics of the actual clock distribution path, allowing the phase detector to receive already-compensated signals before final synchronization adjustment
2Measurement precision
If the DLL delay line adjustment resolution is increased to improve synchronization precision, then clock signal phase accuracy improves, but the system becomes more sensitive to component performance variations causing increased jitter
Solution Approach 1:
The feedback loop continuously monitors the actual clock signal and adjusts the DLL delay line in real-time to compensate for jitter. This closed-loop control allows high-resolution phase detection without amplifying sensitivity to component variations, as the feedback mechanism actively corrects deviations rather than passively responding to them
Solution Approach 2:
The model delay circuit provides beforehand cushioning by pre-compensating for known delay variations in the clock distribution path. This preparatory compensation reduces the impact of component performance variations on the phase detector, allowing high-resolution detection without corresponding increases in jitter sensitivity
3Adaptability or versatility
If signal propagation delay through long signal lines is increased, then more complex circuit layouts are possible, but actual propagation delay varies under changing operating conditions causing clock jitter
Solution Approach 1:
The feedback mechanism captures the actual clock signal after it has traversed the physical signal paths, including all propagation delays through long signal lines. By measuring the actual delayed signal and feeding it back to the phase detector, the system automatically compensates for variations in propagation delay caused by changing operating conditions, thereby maintaining synchronization despite layout flexibility
Solution Approach 2:
The patent dynamically adjusts the DLL delay line parameters in response to feedback from the phase detector. This dynamic parameter adjustment compensates for changes in propagation delay caused by varying operating conditions such as temperature and voltage, maintaining consistent timing despite physical layout constraints
Data Source
AI summary
Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive a reference clock signal and generate an output clock signal having an adjustable phase relationship relative to the reference clock signal, and further includes a clock jitter feedback circuit coupled to a clock tree and the DLL. The clock jitter feedback circuit is configured to synchronize a clock jitter feedback signal and a DLL feedback signal that is based on the output clock signal. The clock jitter feedback circuit is further configured to provide the clock jitter feedback signal to the DLL for synchronization with a buffered reference clock signal. The clock jitter feedback signal is based on and generated in response to receiving a distributed output clock signal from the clock tree circuit and the buffered reference signal is based on the reference clock signal.