Delay Locked Loop Latency Control for Synchronous Semiconductor Timing
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Solution Overview
Problem
Synchronous semiconductor devices face challenges in maintaining latency control margins, particularly in high-frequency environments, due to additional delays on internal command paths compared to clock paths, which reduce the alignment margin between the delay locked clock and internal commands.
Innovation Solution
Incorporating a second delay locked loop that determines a second delay time by reflecting the third delay time generated on the command path, allowing the latency control unit to shift internal commands accordingly, ensuring alignment with the delay locked clock and compensating for additional delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single delay locked loop is used to delay the clock signal, then the clock path delay is compensated, but the additional delay on the internal command path is not accounted for, reducing the latency control margin
Solution Approach 1:
The patent divides the delay compensation function into two separate delay locked loops: one for the clock path and another for the command path. This segmentation allows each DLL to independently compensate for delays specific to its respective path, thereby maintaining accurate timing relationships without requiring a single complex DLL to handle all delay variations.
Solution Approach 2:
The patent introduces an intermediary delay element in the command path that is controlled by the second delay locked loop. This intermediary delay compensates for the additional processing delay introduced by the internal command generation unit, acting as a mediator to balance the timing between clock and command signals.
2Reliability
If the internal command path is simplified to reduce delay, then the latency control margin improves, but the command processing functionality is compromised
Solution Approach 1:
The patent applies preliminary delay compensation through the second delay locked loop before the internal command is processed by the command path. By pre-adjusting the command timing based on the measured delay characteristics, the system maintains accurate timing alignment without requiring simplification of the command processing logic, thus preserving full command processing functionality.
Data Source
AI summary
A synchronous semiconductor device includes an internal command generation unit configured to generate an internal command corresponding to a source command, a delay locked loop configured to delay a source clock by a first delay time required for delay-locking to generate a delay locked clock, a delay time determination unit configured to determine a second delay time for delay-locking the internal command using the source clock, the second delay time being determined by reflecting a third delay time generated on a command path, and a latency control unit configured to shift the internal command by a shifting period, in which the second delay time is reflected, in response to the delay locked clock.