DLL Circuit Power Saving via Latency-Based Sub-Circuit Control
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Solution Overview
Problem
High-speed synchronous semiconductor memory devices face challenges in reducing power consumption due to internal clock skew and latency issues, particularly in DLL circuits, which are critical for low power operation.
Innovation Solution
A semiconductor memory device with a delay locked loop (DLL) circuit and an adaptive power saving decision circuit that calculates an additive latency value to determine which sub-circuits to maintain in a turn-off state during power saving modes, reducing unnecessary power consumption by delaying activation until a read command is received.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DLL circuit operates continuously to maintain clock synchronization, then phase accuracy is improved, but power consumption increases
Solution Approach 1:
The DLL circuit transitions from a static continuous operation state to a dynamic state where it can switch between active and standby modes. The circuit maintains clock synchronization when needed but enters a low-power state when the memory device is in standby mode, thereby reducing power consumption while preserving phase accuracy when operational requirements demand it.
Solution Approach 2:
Instead of continuous operation, the DLL circuit is activated periodically based on the operational state of the memory device. It operates actively during memory access operations and transitions to a standby state during idle periods, creating a periodic on-off pattern that reduces average power consumption while maintaining synchronization capability when needed.
2Use of energy by moving object
If the DLL circuit is turned off to save power, then power consumption is reduced, but clock skew increases
Solution Approach 1:
The DLL circuit is activated in advance before memory access operations begin, allowing it to establish proper clock synchronization and minimize clock skew before actual data operations commence. This preliminary activation ensures that when the circuit is operational, clock skew is already optimized, and the circuit can then enter standby mode to save power during idle periods.
Solution Approach 2:
The circuit dynamically adjusts its operational state based on memory device activity. During standby mode, it consumes minimal power while maintaining the capability to quickly restore proper clock synchronization. When operations are detected, it transitions to an active state to correct and maintain optimal clock skew, thereby balancing power consumption with clock skew stability.
3Speed
If sub-circuits are activated immediately upon receiving an operation command, then response speed is improved, but power consumption increases
Solution Approach 1:
The DLL circuit is activated in advance of actual data operations by detecting operation commands. This preliminary activation allows the circuit to prepare clock synchronization before data access begins, ensuring that when sub-circuits are fully activated, they are already synchronized and can operate at optimal speed without requiring immediate high-power activation that would increase overall power consumption.
Solution Approach 2:
The circuit employs periodic activation based on command detection rather than continuous operation. It remains in a low-power state during idle periods and activates periodically when operation commands are received, thereby reducing average power consumption while maintaining the capability to respond quickly when operational demands arise.
Data Source
AI summary
An operating method of a delay locked loop (DLL) circuit for a semiconductor memory device is disclosed. The DLL circuit may include a plurality of sub-circuits. The method may include calculating an additive latency value based on predetermined parameters, and controlling a set of the plurality of sub-circuits of the DLL circuit to be maintained in a turn-off state based on the calculated additive latency value, during a period of time after the semiconductor device receives an operation command in a power saving mode.