Digital Storage TRIZ Cases

A self powered memory system uses a silicon battery and switch to provide persistent power to volatile memory components.

A control circuit manages memory cell resistance states through iterative voltage application and verification steps.

Adjusting load transistor widths balances read margins, improving signal margin tolerance to noise and process variations.

Dual diodes in a resistive switching memory cell enable precise forward and reverse bias programming, minimizing disturbance to adjacent cells.

Double gate SRAM bitcells connect bitlines to transistor back gates, improving write margin at low voltages and read speed across all voltage levels.

A semiconductor device segments the DLL into a main and replica delay line, allowing the primary circuit to remain inactive while the ODT function operates.

A repair logic circuit maps data using a bad column table to manage defective columns across the entire memory plane.

Local capacitors decouple from gate nodes during sense operations, maintaining stable voltage differences despite power delivery network noise.

A memory controller scales request bandwidth to match data width across multiple independent devices.

Reversing read voltage polarity in phase change memory cells suppresses recovery time after programming.

Stacking perpendicular conductive lines reduces programming current and improves sensing accuracy in three dimensional memory arrays.

Current compensation circuit draws leakage current from selected word lines to stabilize sensing margins in resistance-based memory arrays.

Sense amplifier circuit adjusts voltage levels via shift current to maintain read accuracy despite narrowed resistance state intervals in shrinking MRAM cells.

Independent voltage control on shared storage nodes allows a single 6T cell to serve two ports, eliminating extra transistors and reducing chip area.

A refresh signal generating circuit controls clock, command address, and chip select buffers via a flag signal generator to manage their operational states.

Time-multiplexed global select pins reduce external I/O pin counts while maintaining full access to stacked memory ranks through counter decoding.

Switching circuit disconnects positive feedback during writes to resolve stability versus write ability trade-off in subthreshold SRAM operation.

A correlated electron switch leverages Mott transitions to enable abrupt conductor-insulator state changes.

Calculating additive latency allows the adaptive circuit to keep DLL sub-circuits dormant, resolving the trade-off between phase accuracy and power consumption.

A memory controller validates temperature readings using error-correcting code checks to ensure accurate thermal management decisions.

Segmented transfer circuit units serialize data signals, reducing layout area while maintaining high transfer speed.

A memory system activates adjacent word lines when a target line reaches an activation threshold to refresh connected cells.

A semiconductor memory device manages row hammer effects by repurposing repair controllers to store access addresses for intensive row detection.

A bit line sense amplifier uses a latching unit and control unit to generate pre-charge voltages without external bias sources.

Configurable physical banks in a semiconductor memory device double storage capacity while maintaining compliance with standardized package sizes.

A semiconductor memory device employs a control unit to select memory cells using oblique patterns that avoid sharing bit lines or word lines with previously operated cells.

Continuous-time linear equalizer circuit with source follower delay buffer generates differential intermediate signal for high sensitivity slicer.

A redundancy cell test controller selects all redundancy cells via external commands, ensuring only non-defective units replace faulty regular cells.

A refresh control circuit identifies frequent row addresses to prioritize data recovery operations.

Vertical layer separation reduces coupling between read and write data buses while halving the required layout width in the Y-direction.

Dual refresh periods minimize power consumption by skipping unnecessary operations for inactive cells while maintaining data accuracy.

A memory controller programs a programmable delay line to adjust command signal timing using an automated write leveling procedure.

Segmented nitride layers shield magnetic tunnel junctions from over-etching while enabling reliable electrical connections.

A burst indicator generator creates separate waveforms to isolate command bursts within semiconductor memory systems.

A tipped interface structure focuses electric fields to localize conductive filament formation in resistive memory cells.

A semiconductor memory device uses a shared redundancy unit to pool repair resources across main memory banks.

A single MBIST controller transmits test signals through a high-speed network-on-chip bus to multiple memory circuits.

Separate read operations isolate interfering cells, allowing error correction codes to cancel signal distortion and improve storage reliability.

A memory system path selector reconfigures channel connections to isolate faults within the hardware architecture.

A semiconductor storage device uses a control circuit to switch sense amplifier configurations between single and twin cell modes.

A nonvolatile semiconductor memory device applies differentiated bias potentials to unselected word lines based on their spatial position within the array.

Segmented access paths allow reliable high-voltage domain operation while protecting transistors from excessive stress, preventing Single Event Upsets.

Dynamic voltage adjustment reduces leakage current during self-refresh, extending retention periods while maintaining normal mode reliability.

A semiconductor device uses a flag shifting circuit to generate shifted flag signals for synchronized auto-pre-charge operations.