Refresh Signal Circuit for Dynamic Buffer Control
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Solution Overview
Problem
Conventional semiconductor memory devices experience unnecessary current consumption during all bank refresh operations due to the continuous enable state of clock and command address buffers, which limits energy efficiency.
Innovation Solution
A refresh signal generating circuit that includes a flag signal generator to control the operation of clock, command address, and chip select signal buffers, disabling them during all bank refresh operations to prevent unnecessary current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock buffer and command address buffer maintain enable state during all bank refresh operation, then normal read/write operations can be performed, but unnecessary current consumption occurs
Solution Approach 1:
The patent implements dynamic control of buffer enable states based on operation type. During all bank refresh operations, the clock buffer and command address buffer are dynamically disabled to reduce current consumption, while during normal read/write operations, they are enabled to ensure operational reliability. This dynamic state transition resolves the contradiction between continuous operation capability and energy efficiency.
Solution Approach 2:
The patent employs periodic enable/disable cycles of the clock buffer and command address buffer synchronized with the refresh operation timing. The buffers are periodically enabled during normal operations and periodically disabled during all bank refresh operations, achieving both operational continuity and reduced energy consumption through rhythmic control.
2Reliability
If all bank refresh signal is generated continuously, then memory cells are refreshed properly, but access for general reading or writing operation is limited in all banks
Solution Approach 1:
The patent segments the memory operation into distinct phases: all bank refresh operations and normal read/write operations. By generating the all bank refresh signal only during designated refresh periods and not during normal operations, the patent ensures proper memory cell refresh while avoiding limitations on general reading and writing access speed.
Solution Approach 2:
The all bank refresh signal is generated periodically at predetermined time intervals rather than continuously. This periodic generation ensures that memory cells receive necessary refreshes while allowing normal read/write operations to proceed at full speed during non-refresh periods, resolving the contradiction between refresh reliability and access productivity.
Data Source
AI summary
A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.