Resistive Switching Memory Diode Select Cell Programming
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Solution Overview
Problem
Current non-volatile memory technologies, such as flash memory, face limitations in power consumption and operational speed, while resistive switching memory technologies like ReRAM and CBRAM offer lower power consumption and higher speeds but require efficient programming and erasing methods to maintain data integrity.
Innovation Solution
A resistive switching memory device with diode selection, where each memory cell includes a first and second diode coupled to a common node and a resistive storage element, allowing for programming to a low resistance state with forward bias and erasing to a high resistance state with reverse bias, using specific voltage configurations to minimize disturbance to other cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If flash memory is used for non-volatile storage, then data retention is achieved, but power consumption is high and operation speed is slow
Solution Approach 1:
The patent employs resistive switching memory cells that utilize changes in resistance states (high resistance and low resistance states) to represent binary data. This resistive switching mechanism enables faster write operations compared to flash memory, while the non-volatile nature maintains data retention without continuous power, thereby improving both operation speed and reducing power consumption.
2Productivity
If resistive switching memory is used to reduce power and increase speed, then programming and erasing operations may disturb adjacent cells, but data integrity is compromised
Solution Approach 1:
The memory array is organized into multiple blocks, with each block containing multiple pages of memory cells. This segmentation allows selective programming and erasing of specific pages within blocks, enabling precise control over which cells are affected during operations. By targeting only the intended page, adjacent cells in other pages or blocks remain undisturbed, maintaining data integrity while achieving efficient programming and erasing.
Solution Approach 2:
The patent implements local quality through selective voltage application to specific word lines and bit lines corresponding to the target page. Only the memory cells at the intersection of selected word lines and bit lines receive the programming or erasing voltage, while other cells maintain their original state. This localized approach ensures that programming or erasing operations affect only the intended cells without disturbing adjacent cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient programming and erasing of resistive switching memory cells with reduced power consumption and increased operational speed, while maintaining data integrity by minimizing disturbance to other cells in the memory array.
Implementation Method 1
a first diode having an anode coupled to a first word line and a cathode coupled to a common node; (ii) a second diode having an anode coupled to the common node and a cathode coupled to a second word line
Implementation Method 2
a resistive storage element having an anode coupled to a bit line and a cathode coupled to the common node, wherein the resistive memory cell is configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction
Implementation Method 3
to be erased to a high resistance state by application of an erase voltage in a reverse bias direction
Data Source
AI summary
A resistive switching memory device can include a plurality of resistive memory cells, where each of the resistive memory cells includes: (i) a first diode having an anode coupled to a first word line and a cathode coupled to a common node; (ii) a second diode having an anode coupled to the common node and a cathode coupled to a second word line; and (iii) a resistive storage element having an anode coupled to a bit line and a cathode coupled to the common node, wherein the resistive memory cell is configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction, and to be erased to a high resistance state by application of an erase voltage in a reverse bias direction.