Semiconductor Memory Row Hammer Management Using Repair Controllers
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Solution Overview
Problem
In semiconductor memory devices, the row hammer effect leads to data loss due to charge leakage in frequently accessed memory cell rows, requiring frequent refresh operations, which increases power consumption and chip size overhead, and existing solutions burden the memory controller with hammer refresh operations.
Innovation Solution
A semiconductor memory device that manages row hammer by using a portion of the repair control circuit as a storage resource to store access addresses, determining hammer addresses based on access counts, and performing refresh operations on adjacent memory cell rows, thereby enhancing efficiency without increasing the size of the row hammer management circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated row hammer management circuit is implemented to store access addresses and perform hammer refresh operations, then row hammer management efficiency is improved, but chip size overhead increases
Solution Approach 1:
The repair control circuit, originally designed for defect repair, is made multi-functional by enabling it to also store access addresses for row hammer management. The repair controllers can operate in two modes: storing defective addresses for repair operations or storing access addresses for counting and hammer detection. This eliminates the need for a separate dedicated row hammer management circuit, thereby improving chip size efficiency while maintaining row hammer management capability.
2Reliability
If frequent refresh operations are performed on victim memory cell rows to prevent charge leakage, then data retention reliability is improved, but power consumption increases
Solution Approach 1:
The system implements feedback-based refresh control by continuously monitoring access addresses through the repair controllers. When a hammer address is detected (an address that has been accessed a threshold number of times), the system automatically triggers hammer refresh operations on the corresponding victim rows. This feedback mechanism ensures that refresh operations are performed only when necessary, rather than continuously, thereby maintaining data retention reliability while minimizing unnecessary power consumption.
Solution Approach 2:
The system performs preliminary detection of hammer addresses by counting access patterns before charge loss occurs. By monitoring access addresses in advance and identifying potential hammer addresses when they reach a threshold count, the system can proactively perform refresh operations on victim rows before charge leakage causes data loss. This preliminary action approach prevents data loss while avoiding continuous or excessive refresh operations.
3Adaptability or versatility
If the memory controller is responsible for performing hammer refresh operations, then control flexibility is improved, but the burden on the memory controller increases
Solution Approach 1:
The semiconductor memory device performs self-service for row hammer management by implementing the access address storage, counting, and hammer detection functions internally using the repair control circuit. The memory device autonomously monitors its own access patterns, detects hammer addresses, and triggers hammer refresh operations without requiring external memory controller intervention. This transfers the operational burden from the memory controller to the memory device itself, reducing the controller's workload while maintaining control flexibility through the device's internal logic.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.