Memory Controller Write Leveling for Command Skew Training
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Solution Overview
Problem
Current methods for training command signals in memory qualification and validation are cumbersome, error-prone, and time-consuming, especially as DRAM frequency increases, making it difficult to achieve skew compensation across the entire silicon process range.
Innovation Solution
A method and system for automatically training skew between command and clock signals using the write leveling mechanism, which programs a memory controller to operate in a specific mode, initializes a programmable delay line, and performs a write leveling procedure to determine if a memory module is in a pass or error state, allowing for adjustment of command signal delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual trace extraction and software algorithm methods are used for command signal training, then skew compensation can be achieved, but the process becomes cumbersome, error-prone, and time-consuming
Solution Approach 1:
The memory module performs self-training by automatically determining its own timing parameters through the write leveling procedure. The module uses its internal logic to sample commands at different delays and autonomously identify the optimal skew compensation values, eliminating the need for external manual measurement and software processing.
Solution Approach 2:
The manual mechanical process of trace extraction and software-based skew compensation is replaced with an automated electrical signaling process. The write leveling mechanism uses electrical signals to automatically probe and determine timing parameters, substituting the mechanical/software approach with a direct hardware-based self-testing method.
2Measurement precision
If manual trace extraction tools and software algorithms are used for every board type and memory configuration, then skew compensation is achieved, but the process is repeated unnecessarily for each configuration
Solution Approach 1:
The write leveling mechanism is designed to be universally applicable across different board types, memory configurations, and DRAM frequencies. The same automated procedure can be used for all configurations, making the training process multi-functional and eliminating the need for separate manual processes for each variant.
Solution Approach 2:
The system automatically adapts to different configurations by changing its operating parameters during the write leveling procedure. The memory module can adjust its sampling timing and delay values based on the specific board and memory configuration, allowing a single universal procedure to handle multiple scenarios without manual reconfiguration.
3Speed
If DRAM frequency increases, then data throughput improves, but the command and clock eye width decreases making skew compensation increasingly difficult
Solution Approach 1:
The memory module performs self-measurement of the command eye width at its own internal timing points. By using its internal logic to sample and evaluate commands at different delays, the module automatically determines the optimal timing without requiring external measurement equipment, thus overcoming the difficulty of measuring decreasing eye width at higher frequencies.
Solution Approach 2:
The write leveling mechanism incorporates feedback loops where the memory module's response to sampled commands is used to adjust and refine the timing measurements. This feedback allows the system to accurately determine skew compensation values even as the command eye width decreases with increasing frequency, by iteratively probing and responding to the actual signal conditions.
Data Source
AI summary
A method of training a command signal for a memory module. The method includes programming a memory controller into a mode where a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response to the write leveling procedure is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.