Semiconductor Memory Cell Selection Pattern for Leak Current Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistance varying memory devices face issues with increased leak current in unselected memory cells, leading to malfunction and higher power consumption due to reverse recovery currents and residual charges after setting or resetting operations.
Innovation Solution
The semiconductor memory device employs a control unit that selects memory cells in a manner that avoids unselected cells sharing bit lines or word lines with previously operated cells, allowing for oblique or zigzag selection patterns to minimize the impact of reverse recovery currents and residual charges, thereby preventing malfunctions and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory cell selection is used, then memory operation can be performed, but leak current increases causing malfunction and high power consumption
Solution Approach 1:
The control unit performs preliminary planning of the selection sequence to avoid selecting memory cells that share bit lines or word lines with previously operated cells. By anticipating and preventing the generation of reverse recovery currents and residual charges through careful selection sequence design, the patent eliminates leak current issues before they occur, ensuring reliable memory operation without excessive power consumption.
2Speed
If memory cells are selected consecutively without considering selection pattern, then operation speed is maintained, but reverse recovery currents cause malfunctions
Solution Approach 1:
The control unit pre-plans the selection sequence to skip memory cells that would be affected by reverse recovery currents from previous operations. This preliminary arrangement allows continuous operation without speed reduction while preventing malfunctions by avoiding problematic cell selections, thus maintaining both high speed and high reliability.
Solution Approach 2:
The patent implements a skipping mechanism where the control unit intentionally skips over memory cells that share bit lines or word lines with previously operated cells. This skipping approach allows the system to rush through the memory array efficiently while bypassing cells that would cause malfunctions due to residual charges, maintaining operation speed without sacrificing accuracy.
3Use of energy by stationary object
If selection sequence is optimized to avoid reverse recovery effects, then power consumption is reduced, but selection complexity increases
Solution Approach 1:
The control unit performs preliminary planning of the selection sequence to minimize power consumption by avoiding cells that would generate leak currents. This pre-planning approach consolidates the complexity into a single control unit that manages the selection pattern, rather than requiring complex hardware modifications across the entire memory system, thus reducing power consumption with controlled complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents mistaken operations, suppresses power consumption, and quickens operation speed by ensuring that the next memory cell selection does not receive effects from reverse recovery currents or residual charges, enhancing the reliability and efficiency of setting, resetting, and reading operations.
Implementation Method 1
a voltage is applied to the selected memory cell to cause flow of a current sufficient to cause a resistance change of the variable resistance element
Data Source
AI summary
This semiconductor memory device comprises: a memory cell array including plural bit lines, plural word lines intersecting the plurality of bit lines, and memory cells provided at intersections of the plural bit lines and the plural word lines; and a control unit operative to control a voltage applied to the bit line and the word line. The control unit, when performing a certain operation consecutively on a plurality of the memory cells, selects a first bit line selected from among the plural bit lines and a first word line selected from among the plural word lines to perform a first operation on a first memory cell. Then, in a subsequent second operation following this first operation, selects a second bit line different from the first bit line and a second word line different from the first word line to select a second memory cell.