Semiconductor Data Bus Layout Using Vertical Layer Separation
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Solution Overview
Problem
The arrangement of hundreds of read and write data buses in semiconductor memory devices, such as DRAM, poses challenges in terms of layout and signal quality due to potential coupling between wiring layers, which can degrade performance.
Innovation Solution
The use of a double-layer wiring structure for read and write data buses, with specific configurations to reduce coupling by arranging them adjacent to each other in the vertical and planar directions, and employing different wiring layers for varying lengths and positions to minimize interference, along with the strategic placement of shield patterns to further reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If read data buses and write data buses are arranged in the same wiring layer, then the layout area is reduced, but coupling between buses increases causing signal quality degradation
Solution Approach 1:
The patent applies dimensionality change by transitioning from a single-plane wiring arrangement to a multi-layer wiring structure. Read data buses are arranged in a first wiring layer while write data buses are arranged in a second wiring layer, vertically separating the two types of buses. This spatial separation in the vertical dimension reduces electromagnetic coupling between read and write buses while maintaining compact horizontal layout, thus resolving the contradiction between area efficiency and signal quality.
2Object-affected harmful factors
If shield patterns are added between read and write data buses, then coupling is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of adding shield patterns that would increase device complexity, the patent uses the vertical dimension (multiple wiring layers) to separate read and write data buses. This approach achieves coupling reduction through natural spatial separation rather than adding extra shielding elements, thereby maintaining manufacturing simplicity while effectively reducing electromagnetic interference.
3Object-affected harmful factors
If hundreds of read and write data buses are arranged separately, then signal quality is maintained, but the required wiring width and layout area increase
Solution Approach 1:
The patent resolves the contradiction by utilizing the vertical dimension through multi-layer wiring. Read data buses occupying the first wiring layer and write data buses occupying the second wiring layer allow both sets of buses to be densely packed in the horizontal plane without increasing overall wiring width, while the vertical separation maintains signal quality by preventing coupling.
4Object-affected harmful factors
If read and write data buses are arranged adjacent to each other in the vertical direction, then coupling is reduced, but the planar layout becomes more complex
Solution Approach 1:
The patent simplifies the layout complexity by systematically assigning read data buses to the first wiring layer and write data buses to the second wiring layer. This regular alternating pattern in the vertical dimension creates a predictable and manageable layout structure, making the design process more systematic rather than more complex, while effectively reducing coupling between adjacent buses.
Data Source
AI summary
An apparatus that includes: a plurality of first data amplifiers arranged in line in a first direction; a plurality of first read data buses each coupled to a corresponding one of the plurality of first data amplifiers, the plurality of first read data buses having different lengths one another; and a plurality of first write data buses each coupled to the corresponding one of the plurality of first data amplifiers, the plurality of first write data buses having different lengths one another. The plurality of first read data buses and the plurality of first write data buses are alternately arranged in parallel in a second direction vertical to the first direction. The plurality of first read data buses are arranged in longest order and the plurality of first write data buses are arranged in shortest order.